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document number: 309823-005us november 2006 intel strataflash ? cellular memory (m18) datasheet product features ? high-performance read, program and erase ? 96 ns initial read access ? 512-mbit, 1-gbit device: 108 mhz with zero wait-state synchronous burst reads: 7 ns clock-to-data output ? 256-mbit device: 133 mhz with zero wait- state synchronous burst reads: 5.5 ns clock-to-data output ? 8-, 16-, and continuous-word synchronous-burst reads ? programmable wait configuration ? customer-configurable output driver impedance ? buffered enhanced factory programming: 3.2 s/word (typ), 65 nm; 4.2 s/word (typ), 90 nm ? block erase: 0.9 s per block (typ) ? 20 s (typ) program suspend ? 20 s (typ) erase suspend ? architecture ? 16-bit wide data bus ? multi-level cell technology ? symmetrically-blocked array architecture ? 256-kbyte erase blocks ? 1-gbit device: eight 128-mbit partitions ? 512-mbit device: eight 64-mbit partitions ? 256-mbit device: eight 32-mbit partitions. ? read-while-program and read-while-erase ? status register for partition/device status ? blank check feature ? quality and reliability ? expanded temperature: ?30 c to +85 c ? minimum 100,000 erase cycles per block ? etox? x process technology (65 nm) ? etox? ix process technology (90 nm) ? power ? core voltage: 1.7 v - 2.0 v ? i/o voltage: 1.7 v - 2.0 v ? standby current: 70 a (typ), 65 nm ? standby current: 50 a (typ), 90 nm ? deep power-down mode: 2 a (typ) ? automatic power savings mode ? 16-word synchronous-burst read current: 23 ma (typ) @ 108 mhz ? software ?intel ? flash data integrator (intel ? fdi) optimized ? basic command set and extended command set compatible ? common flash interface ? security ? otp registers: 64 unique pre-programmed bits 2112 user-programmable bits ? absolute write protection with v pp = gnd ? power-transition erase/program lockout ? individual zero-latency block locking ? individual block lock-down ? density and packaging ? density: 1 gbit, 512 mbit, 256 mbit ? address-data multiplexed and non- multiplexed interfaces ? x16d (105-ball) flash scsp ? x16c (107-ball) flash scsp ? 0.8 mm pitch lead-free solder-ball
intel strataflash ? cellular memory (m18) ds november 2006 2 document number: 309823-005us legal lines and disc laim ers information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. intel may make changes to specifications and product descriptions at any time, without notice. intel corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature may be obtained b y calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com . intel and intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2006, intel corporation. all rights reserved.
intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 3 intel strataflash ? cellular memory (m18) contents 1.0 introduction .............................................................................................................. 7 1.1 document purpose .............................................................................................. 7 1.2 nomenclature ..................................................................................................... 7 1.3 acronyms........................................................................................................... 7 1.4 conventions ....................................................................................................... 8 2.0 functional description ............................................................................................... 9 2.1 product overview ................................................................................................ 9 2.2 configuration and memory map ........................................................................... 10 2.3 device id ......................................................................................................... 11 2.4 ordering information ......................................................................................... 12 2.5 additional information ....................................................................................... 13 3.0 package information ............................................................................................... 14 4.0 ballout and signal descriptions ............................................................................... 23 4.1 signal ballouts x16d.......................................................................................... 23 4.1.1 x16d (105-ball) ballout, non-mux ............................................................ 23 4.1.2 x16d (105-ball) ballout, ad-mux.............................................................. 24 4.2 signal descriptions x16d.................................................................................... 25 4.3 signal ballouts x16c .......................................................................................... 29 4.3.1 x16c (107-ball) ballout, non-mux ............................................................ 29 4.3.2 x16c (107-ball) ballout, ad-mux .............................................................. 30 4.4 signal descriptions x16c .................................................................................... 31 4.5 signal ballouts x16 split bus............................................................................... 34 4.5.1 x16 split bus (165-ball) ballout, non-mux ................................................. 34 4.6 signal descriptions x16 split bus......................................................................... 35 5.0 maximum ratings and operating conditions ............................................................ 39 5.1 absolute maximum ratings................................................................................. 39 5.2 operating conditions ......................................................................................... 40 6.0 electrical characteristics ......................................................................................... 41 6.1 dc current specifications ................................................................................... 41 6.2 dc voltage specifications ................................................................................... 43 6.3 capacitance...................................................................................................... 44 7.0 nor flash ac characteristics ................................................................................... 45 7.1 ac test conditions ............................................................................................ 46 7.2 read specifications............................................................................................ 47 7.2.1 timings: non mux device, async read ...................................................... 50 7.2.2 timings: non mux device, sync read, 512-mbit, 1-gbit, 108 mhz................. 51 7.2.3 timings: non mux device, sync read, 256-mbit, 133 mhz ........................... 53 7.2.4 timings: ad-mux device, async read ....................................................... 55 7.2.5 timings: ad-mux device, sync read, 512-mbit, 1-gbit, 108 mhz .................. 55 7.2.6 timings: ad-mux device, sync read, 256-mbit, 133 mhz ............................ 57 7.3 write specifications ........................................................................................... 59 7.3.1 timings: non mux device, async write...................................................... 60 7.3.2 timings: non mux device, sync write, 512-mbit, 1-gbit, 108 mhz ................ 61 7.3.3 timings: non mux device, sync write, 256-mbit, 133 mhz ........................... 62 7.3.4 timings: ad-mux device, async write ....................................................... 63 7.3.5 timings: ad-mux device, sync write, 512-mbit, 1-gbit, 108 mhz ................. 65 7.3.6 timings: ad-mux device, sync write, 256-mbit, 133 mhz ............................ 66 7.4 program and erase characteristics....................................................................... 67 7.5 reset specifications........................................................................................... 69
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 4 document number: 309823-005us 7.6 deep power down specifications..........................................................................70 figures 1 mechanical specifications for x16d (105-ball) package (8x10x1.0 mm)............................15 2 mechanical specifications for x16d (105-ball) package (8x10x1.4 mm)............................16 3 mechanical specifications for x16d (105-ball) package (9x11x1.2 mm)............................17 4 mechanical specifications for x16d (105 balls) package (11x15x1.2 mm).........................18 5 mechanical specifications for x16 split bus (165-ball) package (10x11x1.2 mm)...............19 6 mechanical specifications for x16c (107-ball) package (8x10x1.2 mm)............................20 7 mechanical specifications for x16c (107-ball) package (8x11x1.2 mm)............................21 8 mechanical specifications for x16c (107-ball) package (11x11x1.2 mm) ..........................22 9 x16d (105-ball) electrical ballout, non-mux .................................................................23 10 x16d (105-ball) electrical ballout, ad-mux ..................................................................24 11 x16c (107-ball) electrical ballout, non-mux .................................................................29 12 x16c (107-ball) electrical ballout, ad-mux...................................................................30 13 x16 split bus (165 active ball) electrical ballout, non-mux .............................................34 14 timing symbol notation convention............................................................................45 15 ac input/output reference waveform.........................................................................46 16 transient equivalent testing load circuit .....................................................................46 17 clock input ac waveform ..........................................................................................47 18 async single-word read: adv# latch.........................................................................50 19 async page-mode read timing ...................................................................................51 20 sync single-word array/non-array read, 512-mbit, 1-gbit, 108 mhz ..............................51 21 continuous burst read: output delay at eowl, 512-mbit, 1-gbit, 108 mhz......................52 22 sync burst-mode unaligned 8-word burst read, 512-mbit, 1-gbit, 108 mhz .....................52 23 sync array/non-array read, 256-mbit, 133 mhz...........................................................53 24 sync array/non-array read: adv# max low pulse width, 256-mbit, 133 mhz ..................53 25 continuous burst read: output delay at eowl, 256-mbit, 133 mhz ................................54 26 sync burst-mode unaligned 8-word burst read, 256-mbit, 133 mhz................................54 27 async word read .....................................................................................................55 28 sync single-word array/non-array read, 512-mbit, 1-gbit, 108 mhz ..............................55 29 continuous burst read: output delay at eowl, 512-mbit, 1-gbit, 108 mhz......................56 30 sync burst-mode unaligned 16-word burst read, 512-mbit, 1-gbit, 108 mhz ...................56 31 sync array or non-array read, 256-mbit, 133 mhz .......................................................57 32 sync unaligned 8-word burst read: adv# max low pulse width, 256-mbit, 133 mhz ........57 33 continuous burst read: output delay at eowl, 256-mbit, 133 mhz ................................58 34 write to write ..........................................................................................................60 35 async read to write .................................................................................................60 36 write to async read .................................................................................................61 37 sync read to write, 512-mbit, 1-gbit, 108 mhz ............................................................61 38 write to sync read, 512-mbit, 1-gbit, 108 mhz ............................................................62 39 sync read to write, 256-mbit, 133 mhz.......................................................................62 40 write to sync read, 256-mbit, 133 mhz.......................................................................63 41 write to write ..........................................................................................................63 42 async read to write .................................................................................................64 43 write to async read .................................................................................................64 44 sync read to write, 512-mbit, 1-gbit, 108 mhz ............................................................65 45 write to sync read, 512-mbit, 1-gbit, 108 mhz ............................................................65 46 sync read to write, 256-mbit, 133 mhz.......................................................................66 47 write to sync read, 256-mbit, 133 mhz.......................................................................66 48 reset operation timing .............................................................................................69 49 deep power down operation timing ...........................................................................70 50 reset during deep power down operation timing.........................................................70
intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 5 intel strataflash ? cellular memory (m18) tables 1 definition of terms..................................................................................................... 7 2 list of acronyms ........................................................................................................ 7 3 datasheet conventions ............................................................................................... 8 4 main array memory map ........................................................................................... 10 5 device id codes, 90 nm ............................................................................................ 11 6 device id codes, 65 nm ............................................................................................ 11 7 ordering information ................................................................................................ 12 8 signal descriptions, x16d non-mux / x16d ad-mux ballout ........................................... 25 9 signal descriptions for x16c / x16c ad-mux ballout ..................................................... 31 10 signal descriptions, x16 split bus, non-mux ................................................................ 35 11 absolute maximum ratings ....................................................................................... 39 12 operating conditions ................................................................................................ 40 13 dc current specifications, 90 nm and 65 nm ............................................................... 41 14 dc voltage specifications .......................................................................................... 43 15 capacitance ............................................................................................................ 44 16 codes for timing signals and timing states................................................................. 45 17 ac input requirements ............................................................................................. 46 18 test configuration component value for worst case speed conditions ............................ 46 19 ac read, 512-mbit, 1-gbit, 108 mhz, vccq = 1.7 v to 2.0 v ......................................... 47 20 ac read, 256-mbit, 133 mhz, vccq = 1.7 v to 2.0 v.................................................... 49 21 ac write specifications ............................................................................................. 59 22 program-erase characteristics, 256-mbit, 512-mbit and 1-gbit ....................................... 67 23 reset specifications ................................................................................................. 69 24 deep power down specifications ................................................................................ 70
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 6 document number: 309823-005us revision history date revision description 14-april-06 001 initial release 28-april-06 002 updated the template (naming and branding). on the cover page, changed befp from 1.6 s/byte (typ) to 3.2 s/word (typ). 20-june-06 003 correced the befp on the cover page to read 3.2 s/word and synchronized the befp on the cover with that in table 22, ?program-erase characteristics, 256-mbit, 512-mbit and 1-gbit? on page 67 . added figure 1, ?mechanical specifications for x16d (105-ball) package (8x10x1.0 mm)? on page 15 . added the following part numbers to table 7, ?ordering information? on page 12 : ?pf48f6000m0y0be ?pf38f6070m0y0be ?pf38f6070m0y0ve ?pf48f6000m0y1be october 2006 004 removed information on the 90 nm extended flash array (efa) feature that is no longer supported. november 2006 005 revised to include 65 nm, 1-gbit device information. moved sections for device id, additional information, and order information to functional description chapter. created a separate m18 developer?s manual to include the following information: ?bus interface ?flash operations ?device command codes ?flow charts ?common flash interface ?next state table removed line item pf5566mmy0c0 (512+512 m18 + 128 + 128 psram) from ta b l e 7 , ?ordering information? on page 12 and removed its package (8x11x1.4, x16c 107 ball). added the following line items to table 7, ?ordering information? on page 12 : ?pf48f6000m0y0be, 65 nm ?pf38f6070m0y0be, 65 nm ?pf38f4060m0y0b0 ?PF58F0031M0Y1BE, 65 nm ?pf38f6070m0y0c0, 65 nm ?pf38f4060m0y0c0 ?pf38f4060m0y1c0 ?pf38f6070m0y0ve, 65 nm added the following packages to support new line items: ?8x10x1.0, x16d 105 ball ?11x15x1.2, x16d 105 ball ?11x11x1.2, x16c 107 ball ?8x10x1.2, x16c 107 ball ?10x11x1.2, x16sb 165 ball
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 7 1.0 introduction intel strataflash ? cellular memory (m18) is the 6 th generation intel strataflash ? memory with multi-level cell (mlc) technology. it provides high-performance, low- power synchronous-burst read mode and asynchronous read mode at 1.8 v. it features flexible, multi-partition read-while-program and read-while-erase capability, enabling background programming or erasing in one partition simultaneously with code execution or data reads in another partition. the eight partitions allow flexibility for system designers to choose the size of the code and data segments. the intel strataflash ? cellular memory (m18) is manufactured using intel 65 nm etox? x and 90 nm etox? ix process technology and is available in industry-standard chip-scale packaging. 1.1 document purpose this document describes the specifications of the intel strataflash ? cellular memory (m18) device. 1.2 nomenclature 1.3 acronyms table 1. definition of terms term definition 1.8 v refers to vcc and vccq voltage range of 1.7 v to 2.0 v block a group of bits that erase with one erase command main array a group of 256-kb blocks used for storing code or data partition a group of blocks that share common program and erase circuitry and command status register programming region an aligned 1-kb section within the main array segment a 32-byte section within the programming region byte 8 bits word 2 bytes = 16 bits kb 1024 bits kb 1024 bytes kw 1024 words mb 1,048,576 bits mb 1,048,576 bytes table 2. list of acronyms acronym meaning aps automatic power savings cfi common flash interface du don?t use ecr enhanced configuration register (flash)
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 8 document number: 309823-005us 1.4 conventions etox eprom tunnel oxide fdi intel ? flash data integrator rcr read configuration register (flash) rfu reserved for future use scsp stacked chip scale package table 2. list of acronyms acronym meaning table 3. datasheet conventions convention meaning group membership brackets square brackets are used to designate group membership or to define a group of signals with a similar function, such as a[21:1]. vcc vs. v cc when referring to a signal or package-connection name, the notation used is vcc. when referring to a voltage level, the notation used is subscripted such as v cc . device this term is used interchangeably throughout this document to denote either a particular die, or all die in the package. f[3:1]-ce#, f[2:1]-oe# this is the method used to refer to more than one chip-enable or output enable. when each is referred to individually, the reference is f1-ce# and f1-oe# (for die #1), and f2-ce# and f2- oe# (for die #2). f-vcc when referencing flash memory signals, the notation used is f-vcc or f-v cc, respectively. 00ffh denotes 16-bit hexadecimal numbers 00ff 00ffh denotes 32-bit hexadecimal numbers
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 9 2.0 functional description the functional description includes the following sections: ?product overview ? configuration and memory map ? device id ? ordering information ? additional information 2.1 product overview the intel strataflash ? cellular memory (m18) device provides high read and write performance at low voltage on a 16-bit data bus. the flash memory device has a multi-partition architecture with read-while-program and read-while-erase capability. the device supports synchronous burst reads up to 108 mhz using adv# address- latching on the following densities: ? 512-mbit devices ? 1-gbit devices the device supports synchronous burst reads up to 133 mhz using clk address- latching on the following densities: ? 256-mbit devices in continuous-burst mode, a data read can traverse partition boundaries. upon initial power-up or return from reset, the device defaults to asynchronous array- read mode. synchronous burst-mode reads are enabled by programming the read configuration register. in synchronous burst mode, output data is synchronized with a user-supplied clock signal. a wait signal provides easy cpu-to-flash memory synchronization. designed for low-voltage applications, the device supports read operations with v cc at 1.8 v, and erase and program operations with v pp at 1.8 v or 9.0 v. vcc and vpp can be tied together for a simple, ultra-low power design. in addition to voltage flexibility, a dedicated vpp connection provides complete data protection when v pp is less than v pplk . a status register provides status and error conditions of erase and program operations. one-time-programmable (otp) registers allow unique flash device identification that can be used to increase flash content security. also, the individual block-lock feature provides zero-latency block locking and unlocking to protect against unwanted program or erase of the array.
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 10 document number: 309823-005us the flash memory device offers three power savings features: ? automatic power savings (aps) mode: the device automatically enters aps following a read-cycle completion. ? standby mode: standby is initiated when the system deselects the device by deasserting ce#. ? deep power-down (dpd) mode: dpd provides the lowest power consumption and is enabled by programming in the enhanced configuration register. dpd is initiatied by asserting the dpd pin. 2.2 configuration and memory map the intel strataflash ? cellular memory device features a symmetrical block architecture. the flash device main array is divided as follows: ? the main array of the 256-mbit device is divided into eight 32-mbit partitions. each parition is divided into sixteen 256-kbyte blocks: 8 x 16 = 128 blocks in the main array of a 256-mbit device. ? the main array of the 512-mbit device is divided into eight 64-mbit partitions. each parition is divided into thirty-two 256-kbyte blocks: 8 x 32 = 256 blocks in the main array of a 256-mbit device. ? the main array of the 1-gbit device is divided into eight 128-mbit partitions. each parition is divided into sixty-four 256-kbyte blocks: 8 x 64 = 512 blocks in the main array of a 1-gbit device. each block is divided into as many as two-hundred-fifty-six 1-kbyte programming regions. each region is divided into as many as thirty-two 32-byte segments. table 4. main array memory map (sheet 1 of 2) 256-mbit device 512-mbit device 1-gbit device blk# address range blk# address range blk# address range partition 7 32mbit 127 0fe0000-0ffffff 64mbit 255 1fe0000-1ffffff 128mbit 511 3fe0000-3ffffff ... ... ... ... ... ... 112 0e00000-0e1ffff 224 1c00000-1c1ffff 448 3800000-381ffff partition 6 32mbit 111 0de0000-0dfffff 64mbit 223 1be0000-1bfffff 128mbit 447 37e0000-37fffff ... ... ... ... ... ... 96 0c00000-0c1ffff 192 1800000-181ffff 384 3000000-301ffff partition 5 32mbit 95 0be0000-0bfffff 64mbit 191 17e0000-17fffff 128mbit 383 2fe0000-2ffffff ... ... ... ... ... ... 80 0a00000-0a1ffff 160 1400000-141ffff 320 2800000-281ffff partition 4 32mbit 79 09e0000-09fffff 64mbit 159 13e0000-13fffff 128mbit 319 27e0000-27fffff ... ... ... ... ... ... 64 0800000-081ffff 128 1000000-101ffff 256 2000000-201ffff partition 3 32mbit 63 07e0000-07fffff 64mbit 127 0fe0000-0ffffff 128mbit 255 1fe0000-1ffffff ... ... ... ... ... ... 48 0600000-061ffff 96 0c00000-0c1ffff 192 1800000-181ffff partition 2 32mbit 47 05e0000-05fffff 64mbit 95 0be0000-0bfffff 128mbit 191 17e0000-17fffff ... ... ... ... ... ... 32 0400000-041ffff 64 0800000-081ffff 128 1000000-101ffff
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 11 2.3 device id partition 1 32mbit 31 03e0000-03fffff 64mbit 63 07e0000-07fffff 128mbit 127 0fe0000-0ffffff ... ... ... ... ... ... 16 0200000-021ffff 32 0400000-041ffff 64 0800000-081ffff partition 0 32mbit 15 01e0000-01fffff 64mbit 31 03e0000-03fffff 128mbit 63 07e0000-07fffff ... ... ... ... ... ... 0 0000000-001ffff 0 0000000-001ffff 0 0000000-001ffff table 5. device id codes, 90 nm density product device identifier code (hex) 512 mbit non-mux 887e ad-mux 8881 256 mbit non-mux 8901 ad-mux 8904 table 6. device id codes, 65 nm density product device identifier code (hex) 1 gbit non-mux 88b0 ad-mux 88b1 table 4. main array memory map (sheet 2 of 2) 256-mbit device 512-mbit device 1-gbit device blk# address range blk# address range blk# address range
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 12 document number: 309823-005us 2.4 ordering information for combinations not listed, please contact your local intel sales office. note: to order parts listed above and to obtain a datasheet for the m18 scsp parts, please contact your local intel sales office. table 7. ordering information i/o voltage flash (m18) nand ram package part number (v) density (mbit), bus speed: clk and tacc density (mbit), bus density (mbit), type, bus size (mm) ballout x16d shared bus, non-mux 1.8 1024, bus a 108 mhz 96 ns ? ? 8 x 10 x 1.0 x16d 105-ball pf48f6000m0y0be 65 nm 1.8 1024, bus a 108 mhz 96 ns ? 256 lpsdram, bus a 9 x 11 x 1.2 x16d 105-ball pf38f6070m0y0be 65 nm 1.8 512, bus a 108 mhz 96 ns ? 128 lpsdram, bus a 9 x 11 x 1.2 x16d 105-ball pf38f5060m0y0b0 1.8 512, bus a 108 mhz 96 ns ? 256 lpsdram, bus a 9 x 11 x 1.2 x16d 105-ball pf38f5070m0y0b0 1.8 512 + 512, bus a 108 mhz 96 ns ? ? 8 x 10 x 1.4 x16d 105-ball pf48f5500m0y0b0 1.8 256, bus a 133 mhz 96 ns ? 128 lpsdram, bus a 9 x 11 x 1.2 x16d 105-ball pf38f5060m0y0b0 x16d shared bus, ad-mux 1.8 1024, bus a 108 mhz 96 ns 2048, bus a ? 11 x 15 x 1.2 x16d 105-ball PF58F0031M0Y1BE 65 nm 1.8 512 + 512, bus a 108 mhz 96 ns ? ? 8 x 10 x 1.4 x16d 105-ball pf48f5500m0y1b0 x16c, shared bus, non-mux 1.8 1024, bus a 108 mhz 96 ns ? 256 psram, bus a 11 x 11 x 1.2 x16c 107-ball pf38f6070m0y0c0 65 nm 1.8 512, bus a 108 mhz 96 ns ? 128 psram, bus a 8 x 11 x 1.2 x16c 107-ball pf38f5060m0y0c0 1.8 512, bus a 108 mhz 96 ns ? 64 psram, bus a 8 x 11 x 1.2 x16c 107-ball pf38f5050m0y0c0 1.8 256, bus a 133 mhz 96 ns ? 128 psram, bus a 8 x 10 x 1.2 x16c 107-ball pf38f4060m0y0c0 1.8 256, bus a 133 mhz 96 ns ? 64 psram, bus a 8 x 10 x 1.2 x16c 107-ball pf38f4050m0y0c0 x16c, shared bus, ad-mux 1.8 256, bus a 133 mhz 96 ns ? 128 psram, bus a 8 x 10 x 1.2 x16c 107-ball pf38f4060m0y1c0 x16sb, split bus, non-mux 1.8 1024, bus a 108 mhz 96 ns ? 256 lpsdram, bus b 10 x 11 x 1.2 x16sb 165-ball pf38f6070m0y0ve 65 nm
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 13 2.5 additional information order number document/tool 315567 intel strataflash ? cellular memory (m18) developer?s manual 307654 intel strataflash ? cellular memory (m18 scsp); 2048-mbit m18 (non-mux and ad-mux i/o) family with synchronous psram datasheet 310048 designing with intel strataflash ? wireless memory and pre-enabling intel strataflash ? cellular memory, application note 822 309311 intel strataflash ? cellular memory (m18 scsp) to arm ? primecell tm design guide, application note 841 315651 migration guide for intel strataflash ? cellular memory (m18) 90 nm to 65 nm, application note 860 310058 effect of program buffer size on system interrupt latency, application note 816 notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intel?s world wide web home page at http://www.intel.com for technical documentation and tools. 3. for the most current information on intel flash products, visit our website at http://developer.intel.com/design/flash/.
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 14 document number: 309823-005us 3.0 package information the following figures show the ballout package information for the m18 device: ? figure 1, ?mechanical specifications for x16d (105-ball) package (8x10x1.0 mm)? ? figure 2, ?mechanical specifications for x16d (105-ball) package (8x10x1.4 mm)? on page 16 ? figure 3, ?mechanical specifications for x16d (105-ball) package (9x11x1.2 mm)? ? figure 4, ?mechanical specifications for x16d (105 balls) package (11x15x1.2 mm)? on page 18 ? figure 5, ?mechanical specifications for x16 split bus (165-ball) package (10x11x1.2 mm)? ? figure 6, ?mechanical specifications for x16c (107-ball) package (8x10x1.2 mm)? on page 20 ? figure 7, ?mechanical specifications for x16c (107-ball) package (8x11x1.2 mm)? on page 21 ? figure 8, ?mechanical specifications for x16c (107-ball) package (11x11x1.2 mm)? on page 22
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 15 figure 1. mechanical specifications for x16d (105-ball) package (8x10x1.0 mm) dimensions symbol min nom max notes min nom max package heig ht a 1.0 0.0394 ball height a1 0.200 0.0079 package body thicknes s a2 0.660 0.0260 ball (lead) w idth b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body leng th d 9.90 10.00 10.10 0.3898 0.3937 0.3976 package body wid th e 7.90 8.00 8.10 0.3110 0.3150 0.3189 pitch e 0.800 0.0315 ball (lead) count n 105 105 seating plane coplanarity y 0.100 0.0039 corner to ball distance along e s1 0.700 0.800 0.900 0.0276 0.0315 0.0354 corner to ball distance along d s2 0.500 0.600 0.700 0.0197 0.0236 0.0276 note: drawing not to scale. a y a2 a1 pin 1 co rn er d e b a b c d e f g h j k 8 7 6 5 4 3 2 19 l m scs p top v i ew - ba l l s i de down s1 s2 e
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 16 document number: 309823-005us figure 2. mechanical specifications for x16d (105-ball) package (8x10x1.4 mm) dimensions symbol min nom max notes min nom max package height a 1.4 0.0551 ball height a1 0.200 0.0079 package body thickness a2 1.070 0.0421 ball (lead ) w id th b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body length d 9.90 10.00 10.10 0.3898 0.3937 0.3976 packag e bod y w idth e 7.90 8.00 8.10 0.3110 0.3150 0.3189 pitch e 0.800 0.0315 ball (lead ) cou nt n 105 105 seating plane coplanarity y 0.100 0.0039 corn er to ball dis tan ce alon g e s1 0.700 0.800 0.900 0.0276 0.0315 0.0354 corn er to ball dis tan ce alon g d s2 0.500 0.600 0.700 0.0197 0.0236 0.0276 note: drawing not to scale. a y a2 a1 pi n 1 co rn er d e b a b c d e f g h j k 8 7 6 5 4 3 2 19 l m scs p top v i ew - ba l l s i de down s1 s2 e
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 17 figure 3. mechanical specifications for x16d (105-ball) package (9x11x1.2 mm) dimensions symbol min nom max notes min nom max package height a 1.2 0.0472 ball heig ht a1 0.200 0.0079 package body thickness a2 0.860 0. 0339 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body length d 10.90 11.00 11.10 0. 4291 0.4331 0.4370 package body width e 8.90 9.00 9.10 0. 3504 0.3543 0.3583 pitch e 0.800 0.0315 ball (lead) count n 105 105 seating plane coplanarity y 0.100 0.0039 corner to ball dis tance along e s1 1.200 1.300 1.400 0.0472 0.0512 0.0551 corner to ball dis tance along d s2 1.000 1.100 1.200 0.0394 0.0433 0.0472 note: drawing not to scale. a y a2 a1 pin 1 corner d e b a b c d e f g h j k 8 7 6 5 4 3 2 19 l m top view - ball side down s1 s2 e
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 18 document number: 309823-005us figure 4. mechanical specifications for x16d (105 balls) package (11x15x1.2 mm)
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 19 figure 5. mechanical specifications for x16 split bus (165-ball) package (10x11x1.2 mm) millimeters in ches dimensions symbol min nom max notes min nom max package height a 1.2 0.0472 ball height a 1 0.200 0.0079 packag e bod y th icknes s a 2 0.860 0.0339 ball (lead) w idth b 0.325 0.375 0.425 0.0128 0.0148 0.0167 packag e bod y length d 10.90 11.00 11.10 0.4291 0.4331 0.4370 packag e bod y w idth e 9.90 10.00 10.10 0.3898 0.3937 0.3976 pitch e 0.650 0.0256 ball (lead) count n 165 165 seating plane coplanarity y 0.100 0.0039 corner to ball dis tance alo ng e s1 1.325 1.425 1.525 0.0522 0.0561 0.0600 corner to ball dis tance alo ng d s2 1.500 1.600 1.700 0.0591 0.0630 0.0669 note: drawing not to scale. d e b a b c d e f g h j k 8 7 6 5 4 3 2 111 10 9 l m n p r top view - ball side down s1 s2 e a y a2 a1 12 ball one corner
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 20 document number: 309823-005us figure 6. mechanical specifications for x16c (107-ball) package (8x10x1.2 mm) dimensions symbol min nom max notes min nom max package height a 1.2 0.0472 ball heig ht a 1 0.200 0.0079 package body thickness a2 0.860 0.0339 ball (lead) w idth b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body length d 9.90 10.00 10.10 0.3898 0.3937 0.3976 package bo dy w idth e 7.90 8.00 8.10 0.3110 0.3150 0.3189 pitch e 0.800 0.0315 ball (lead) count n 107 107 seatin g plan e co planarity y 0.100 0.0039 corner to ball dis tan ce a lon g e s1 0.700 0.800 0.900 0.0276 0.0315 0.0354 corner to ball dis tan ce a lon g d s2 0.500 0.600 0.700 0.0197 0.0236 0.0276 note: drawing not to scale. a y a2 a1 pi n 1 co rn er d e b a b c d e f g h j k 8 7 6 5 4 3 2 19 l m scs p top view - ball side down s1 s2 e 10
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 21 figure 7. mechanical specifications for x16c (107-ball) package (8x11x1.2 mm) m illimet ers inches dimensions symbol min nom max notes min nom max package height a 1.2 0.0472 ball height a1 0.200 0.0079 package body thickness a2 0.860 0.0339 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package bo dy len gth d 10.90 11.00 11.10 0.4291 0.4331 0.4370 package bo dy wid th e 7.90 8.00 8.10 0.3110 0.3150 0.3189 pitch e 0.800 0.0315 ball (lead) count n 107 107 seating plane cop lanarity y 0.100 0.0039 corner to ball distance along e s1 0.700 0.800 0.900 0.0276 0.0315 0.0354 corner to ball distance along d s2 1.000 1.100 1.200 0.0394 0.0433 0.0472 note: drawing not to scale. a y a2 a1 pin 1 corner d e b a b c d e f g h j k 8 7 6 5 4 3 2 19 l m top view - ball side down s1 s2 e
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 22 document number: 309823-005us figure 8. mechanical specifications for x16c (107-ball) package (11x11x1.2 mm)
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 23 4.0 ballout and signal descriptions this section provides ballout and signal description information for x16d (105-ball), x16c (107-ball), and x16 split bus (165-ball) packages, non-mux, ad-mux interfaces. 4.1 signal ballouts x16d 4.1.1 x16d (105-ball) ballout, non-mux figure 9. x16d (105-ball) electrical ballout, non-mux pin 1 123456789 a du a4 a6 a7 a19 a23 a24 a25 du a b a2 a3 a5 a17 a18 f-dpd a22 a26 a16 b c a1 vss vss vss d-vcc vss vss vss a15 c d a0 s-vcc d-vcc f1-vcc adv# f2-vcc d-vcc n-ale a14 d e f-wp1# we# d2-cs# depop (index) n-cle f4-ce# / a27 a21 a10 a13 e f f-wp2# d1-cs# d-cas# d-ras# depop (rfus) n-re# / s-cs1# a20 a9 a12 f g rfu f2-ce# f1-ce# d-ba0 depop (rfus) d-cke f-rst# a8 a11 g h n-ry/by# n-we# / s-cs2 f3-ce# d-ba1 d-clk# d-we# oe# d-dm1 / s-ub# d-dm0 / s-lb# h j f-vpp vccq vccq f1-vcc d-clk f2-vcc vccq vccq f-wait j k dq2 vss vss vss f-clk vss vss vss dq13 k l dq1 dq3 dq5 dq6 dq7 dq9 dq11 dq12 dq14 l m du dq0 d-ldqs dq4 dq8 dq10 d-udqs dq15 du m 123456789 top view - ball side down reserved for future use do not use de-populated balls active balls legend:
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 24 document number: 309823-005us 4.1.2 x16d (105-ball) ballout, ad-mux figure 10. x16d (105-ball) electrical ballout, ad-mux pin 1 123456789 a du a4 a6 a7 a19 a23 a24 a25 du a b a2 a3 a5 a17 a18 f-dpd a22 a26 a16 b c a1 vss vss vss d-vcc vss vss vss a15 c d a0 s-vcc d-vcc f1-vcc adv# f2-vcc d-vcc n-ale a14 d e f-wp1# we# d2-cs# depop (index) n-cle f4-ce# / a27 a21 a10 a13 e f f-wp2# d1-cs# d-cas# d-ras# depop (rfus) n-re# / s-cs1# a20a9a12 f g rfu f2-ce# f1-ce# d-ba0 depop (rfus) d-cke f-rst# a8 a11 g h n-ry/by# n-we# / s-cs2 f3-ce# d-ba1 d-clk# d-we# oe# d-dm1 / r-ub# d-dm0 / r-lb# h j f-vpp vccq vccq f1-vcc d-clk f2-vcc vccq vccq f-wait j k ad2 vss vss vss f-clk vss vss vss ad13 k l ad1 ad3 ad5 ad6 ad7 ad9 ad11 ad12 ad14 l m du ad0 d-ldqs ad4 ad8 ad10 d-udqs ad15 du m 123456789 top view - ball side down reserved for future use do not use de-populated balls active balls legend:
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 25 4.2 signal descriptions x16d table 8. signal descriptions, x16d non-mux / x16d ad-mux ballout (sheet 1 of 4) symbol type signal descriptions notes address and data signals, non-mux a[max: 0] input address: global device signals. shared address inputs for all memory die during read and write operations. ? 4-gbit: amax = a27 ? 2-gbit: amax = a26 ? 1-gbit: amax = a25 ? 512-mbit: amax = a24 ? 256-mbit: amax = a23 ? 128-mbit: amax = a22 ? a[12:0] are the row and a[9:0] are the column addresses for 512-mbit lpsdram. ? a[12:0] are the row and a[8:0] are the column addresses for 256-mbit lpsdram. ? a[11:0] are the row and a[8:0] are the column addresses for 128-mbit lpsdram. unused address inputs should be treated as rfu. 1 dq[15:0] input/ output data input/outputs: global device signals. dq[15:0] are used to input commands and write-data during write cycles, and to output read-data during read cycles. during nand accesses, dq[7:0] are used to input commands, address-data, and write-data, and to output read-data. data signals are high-z when the device is deselected or its output is disabled. f-adv# input flash address valid: flash-specific signal; low-true input. during synchronous flash read operations, the address is latched on the rising edge of f-adv#, or on the first rising edge of f-clk after f-adv# goes low for devices that support up to 108 mhz, or on the last rising edge of f-clk after f-adv# goes low for devices that support up to 133 mhz. in an asynchronous flash read operation, the address is latched on the rising edge of f-adv# or continuously flows through while f-adv# is low. address and data signals, ad-mux a[max:16] input address: global device signals. shared address inputs for all flash and sram memory die during read and write operations. ? 4-gbit: amax = a27 ? 2-gbit: amax = a26 ? 1-gbit: amax = a25 ? 512-mbit: amax = a24 ? 256-mbit: amax = a23 ? 128-mbit: amax = a22 unused address inputs should be treated as rfu. 1 ad[15:0] input / output address-data multiplexed inputs/ outputs: ad-mux flash and sram lower address and data signals; lpsdram data signals. during ad-mux flash and sram write cycles, ad[15:0] are used to input the lower address followed by commands or write-data. during ad-mux flash read cycles, ad[15:0] are used to input the lower address followed by read-data output. during lpsdram accesses, ad[15:0] are used to input commands and write-data during write cycles or to output read-data during read cycles. during nand accesses, ad[7:0] are used to input commands, address, or write-data, and to output read-data. ad[15:0] are high-z when the flash or sram is deselected or its output is disabled. a[15:0] input rfu, except for dram.
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 26 document number: 309823-005us f-adv# input flash address valid: flash-specific signal; low-true input. during synchronous flash read operations, the address is latched on the rising edge of f-adv#, or on the first rising edge of f-clk after f-adv# goes low for devices that support up to 108 mhz, or on the last rising edge of f-clk after f-adv# goes low for devices that support up to 133 mhz. in an asynchronous flash read operation, the address is latched on the rising edge of f-adv#. control signals f[4:1]-ce# input flash chip enable: flash-specific signal; low-true input. when low, f-ce# selects the associated flash memory die. when high, f-ce# deselects the associated flash die. flash die power is reduced to standby levels, and its data and f-wait outputs are placed in a high-z state. ? f1-ce# is dedicated to flash die #1. ? f[4:2]-ce# are dedicated to flash die #4 through #2, respectively, if present. otherwise, any unused flash chip enable should be treated as rfu. ? for nor/nand stacked device, f1-ce# selects nor die #1, f2-ce# selects nor die #2 while f4-ce# selects nand die #1 and nand die #2 using virtual chip- select scheme, f3-ce# selects nand die #3 if present. 1 f-clk input flash clock: flash-specific signal; rising active-edge input. f-clk synchronizes the flash with the system clock during synchronous operations. d-clk input lpsdram clock: lpsdram-specific signal; rising active-edge input. d-clk synchronizes the lpsdram and ddr lpsdram with the system clock. 2 d-clk# input ddr lpsdram clock: ddr lpsdram-specific signal; falling active-edge input. d-clk# synchronizes the ddr lpsdram with the system clock. 2 oe# input output enable: flash- and sram-specific signal; low-true input. when low, oe# enables the output drivers of the selected flash or sram die. when high, oe# disables the output drivers of the selected flash or sram die and places the output drivers in high-z. f-rst# input flash reset: flash-specific signal; low-true input. when low, f-rst# resets internal operations and inhibits writes. when high, f-rst# enables normal operation. f-wait output flash wait: flash -specific signal; configurable-true output. when asserted, f-wait indicates invalid output data. f-wait is driven whenever f- ce# and oe# are low. f-wait is high-z whenever f-ce# or oe# is high. we# input write enable: flash- and sram-specific signal; low-true input. when low, we# enables write operations for the enabled flash or sram die. d-we# input lpsdram write enable: lpsdram-specific signal; low-true input. d-we#, together with a[max:0], d-ba[1:0], d-cke, d-cs#, d-cas#, and d-ras#, define the lpsdram command or operation. d-we# is sampled on the rising edge of d-clk. 2 f-wp[2:1]# input flash write protect: flash-specific signals; low-true inputs. when low, f-wp# enables the lock-down mechanism. when high, f-wp# overrides the lock-down function, enabling locked-down blocks to be unlocked with the unlock command. ? f-wp1# is dedicated to flash die #1. ? f-wp2# is common to all other flash dies, if present. otherwise it is rfu. ? for nor/nand stacked device, f-wp1# selects all nor dies, while f-wp2# selects all nand dies. f-dpd input flash deep power-down: flash-specific signal; configurable-true input. when enabled in the ecr, f-dpd is used to enter and exit deep power-down mode. n-cle input nand command latch enable: nand-specific signal; high-true input. when high, n-cle enables commands to be latched on the rising edge of n-we#. 2 n-ale input nand address latch enable: nand-specific signal; high-true input. when high, n-ale enables addresses to be latched on the rising edge of n-we#. 2 table 8. signal descriptions, x16d non-mux / x16d ad-mux ballout (sheet 2 of 4) symbol type signal descriptions notes
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 27 n-re# input nand read enable: nand-specific signal; low-true input. when low, n-re# enables the output drivers of the selected nand die. when high, n- re# disables the output drivers of the selected nand die and places the output drivers in high-z. 2, 4 n-ry/by# output nand ready/busy: nand-specific signal; low-true output. when low, n-ry/by# indicates the nand is busy performing a read, program, or erase operation. when high, n-ry/by# indicates the nand device is ready. 2 n-we# input nand write enable: nand-specific signal; low-true input. when low, n-we# enables write operations for the enabled nand die. 2, 5 d-cke input lpsdram clock enable: lpsdram-specific signal; high-true input. when high, d-cke indicates that the next d-clk edge is valid. when low, d-cke indicates that the next d-clk edge is invalid and the selected lpsdram die is suspended. 2 d-ba[1:0] input lpsdram bank select: lpsdram-specific input signals. d-ba[1:0] selects one of four banks in the lpsdram die. 2 d-ras# input lpsdram row address strobe: lpsdram-specific signal; low-true input. d-ras#, together with a[max:0], d-ba[1:0], d-cke, d-cs#, d-cas#, and d-we#, define the lpsdram command or operation. d-ras# is sampled on the rising edge of d-clk. 2 d-cas# input lpsdram column address strobe: lpsdram-specific signal; low-true input. d-cas#, together with a[max:0], d-ba[1:0], d-cke, d-cs#, d-ras#, and d-we#, define the lpsdram command or operation. d-cas# is sampled on the rising edge of d-clk. 2 d[2:1]-cs# input lpsdram chip select: lpsdram-specific signal; low-true input. when low, d-cs# selects the associated lpsdram memory die and starts the command input cycle. when d-cs# is high, commands are ignored but operations continue. ? d-cs#, together with a[max:0], d-ba[1:0], d-cke, d-ras#, d-cas#, and d- we#, define the lpsdram command or operation. d-cs# is sampled on the rising edge of d-clk. ? d[2:1]-cs# are dedicated to lpsdram die #2 and die #1, respectively, if present. otherwise, any unused lpsdram chip selects should be treated as rfu. 2 d-dm[1:0] input lpsdram data mask: lpsdram-specific signal; high-true input. when high, d-dm[1:0] controls masking of input data during writes and output data during reads. ? d-dm1 corresponds to the data on dq[15:8]. ? d-dm0 corresponds to the data on dq[7:0]. 2, 3 d-udqs d-ldqs input / output lpsdram upper/lower data strobe: ddr lpsdram-specific input/output signals. d-udqs and d-ldqs provide as output the read-data strobes, and as input the write- data strobes. ? d-udqs corresponds to the data on dq[15:8]. ? d-ldqs corresponds to the data on dq[7:0]. 2 s-cs1# s-cs2 input sram chip selects: sram-specific signals; s-cs1# low-true input, s-cs2 high- true input. when both are asserted, s-cs1# and s-cs2 select the sram die. when either is deasserted, the sram die is deselected and its power is reduced to standby levels. 2, 4, 5 s-ub# s-lb# input sram upper/lower byte enables: sram-specific signals; low-true inputs. when low, s-ub# enables dq[15:8] and s-lb# enables dq[7:0] during sram read and write cycles. when high, s-ub# masks dq[15:8] and s-lb# masks dq[7:0]. 2, 3 power signals f-vpp power flash program/erase voltage: flash specific. f-vpp supplies program or erase power to the flash die. table 8. signal descriptions, x16d non-mux / x16d ad-mux ballout (sheet 3 of 4) symbol type signal descriptions notes
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 28 document number: 309823-005us notes: 1. f4-ce# and a27 share the same package ball at location e6. only one signal function is available, depending on the stacked device combination. 2. only available on stacked device combinations with nand, sram, and/or lpsdram die; otherwise, treated as rfu. 3. d-dm[1:0] and s-ub#/s-lb# share the same package balls at locations h8 and h9, respectively. only one signal function for each ball location is available, depending on the stacked device combination. 4. s-cs1# and n-re# share the same package ball at location f6. only one signal function is available, depending on the stacked device combination. 5. s-cs2 and n-we# share the same package ball at location h2. only one signal function is available, depending on the stacked device combination. 6. in stack packages with only one nor flash die, this signal can be left floating. f1-vcc power flash core power supply: flash specific. f1-vcc supplies the core power to the nor flash die. f2-vcc power flash core power supply: flash specific. f2-vcc supplies the core power to either 1) the nor flash die in stack packages with multiple nor flash dies, or 2) nand flash die in stack packages with nor-nand flash dies. 6 vccq power i/o power supply: global device i/o power. vccq supplies the device input/output driver voltage. d-vcc power lpsdram core power supply: lpsdram specific. d-vcc supplies the core power to the lpsdram die. 2 s-vcc power sram power supply: sram specific. s-vcc supplies the core power to the sram die. 2 vss ground device ground: global ground reference for all signals and power supplies. connect all vss balls to system ground. do not float any vss connections. du ? do not use: this ball should not be connected to any power supplies, signals, or other balls. this ball can be left floating. rfu ? reserved for future use: reserved by intel for future device functionality and enhancement. this ball must be left floating. table 8. signal descriptions, x16d non-mux / x16d ad-mux ballout (sheet 4 of 4) symbol type signal descriptions notes
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 29 4.3 signal ballouts x16c 4.3.1 x16c (107-ball) ballout, non-mux figure 11. x16c (107-ball) electrical ballout, non-mux pin 1 123456789 a du n-cle a27 a26 p-vcc f-dpd vss du a b du a4 a18 a19 vss f1-vcc f2-vcc a21 a11 b c n-ale a5 r-lb# a23 vss s-cs2 clk a22 a12 c d vss a3 a17 a24 f-vpp r-we# p1-cs# a9 a13 d e vss a2 a7 a25 f-wp1# adv# a20 a10 a15 e f f-wp2# a1 a6 r-ub# f-rst# f-we# a8 a14 a16 f g vccq a0 dq8 dq2 dq10 dq5 dq13 wait f2-ce# g h vss r-oe# dq0 dq1 dq3 dq12 dq14 dq7 f2-oe# / n-re# h j rfu s-cs1# / n-we# f1-oe# dq9 dq11 dq4 dq6 dq15 vccq j k f4-ce# f1-ce# p2-cs# f3-ce# s-vcc p-vcc f2-vcc vccq p-mode# / p-cre k l rfu vss vss vccq f1-vcc vss vss vss vss l m du n-ry/by# rfu rfu rfu rfu rfu rfu du m 123456789 legend: reserved for future use do not use top view - ball side down active balls
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 30 document number: 309823-005us 4.3.2 x16c (107-ball) ballout, ad-mux figure 12. x16c (107-ball) electrical ballout, ad-mux pin 1 123456789 a du n-cle a27 a26 p-vcc f-dpd vss du a b du rfu a18 a19 vss f1-vcc f2-vcc a21 rfu b c n-ale rfu r-lb# a23 vss s-cs2 clk a22 rfu c d vss rfu a17 a24 f-vpp r-we# p1-cs# rfu rfu d e vss rfu rfu a25 f-wp1# adv# a20 rfu rfu e f f-wp2# rfu rfu r-ub# f-rst# f-we# rfu rfu a16 f g vccq rfu ad8 ad2 ad10 ad5 ad13 wait f2-ce# g h vss r-oe# ad0 ad1 ad3 ad12 ad14 ad7 f2-oe# / n-re# h jrfu s-cs1# / n-we# f1-oe#ad9ad11ad4 ad6ad15vccq j k f4-ce# f1-ce# p2-cs# f3-ce# s-vcc p-vcc f2-vcc vccq p-mode# / p-cre k l rfu vss vss vccq f1-vcc vss vss vss vss l m du n-ry/by# rfu rfu rfu rfu rfu rfu du m 123456789 top view - ball side down legend: active balls reserved for future use do not use
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 31 4.4 signal descriptions x16c table 9. signal descriptions for x16c / x16c ad-mux ballout (sheet 1 of 3) symbol type signal descriptions notes address and data signals, non-mux a[max:0] input address: global device signals. shared address inputs for all memory die during read and write operations. ? 4-gbit: amax = a27? 128-mbit: amax = a22 ? 2-gbit: amax = a26? 64-mbit: amax = a21 ? 1-gbit: amax = a25? 32-mbit: amax = a20 ? 512-mbit: amax = a24? 16-mbit: amax = a19 ? 256-mbit: amax = a23? 8-mbit: amax = a18 unused address inputs should be treated as rfu. dq[15:0] input / output data input/outputs: global device signals. inputs data and commands during write cycles, outputs data during read cycles. data signals are high-z when the device is deselected or its output is disabled. adv# input address valid: flash- and synchronous psram-specific signal; low-true input. during synchronous flash read operations, the address is latched on the rising edge of f-adv#, or on the first rising edge of f-clk after f-adv# goes low for devices that support up to 108 mhz, or on the last rising edge of f-clk after f-adv# goes low for devices that support up to 133 mhz. in an asynchronous flash read operation, the address is latched on the rising edge of adv# or continuously flows through while adv# is low. address and data signals, ad-mux a[max:16] input address: global device signals. shared address inputs for all memory die during read and write operations. ? 4-gbit: amax = a27? 128-mbit: amax = a22 ? 2-gbit: amax = a26? 64-mbit: amax = a21 ? 1-gbit: amax = a25? 32-mbit: amax = a20 ? 512-mbit: amax = a24? 16-mbit: amax = a19 ? 256-mbit: amax = a23? 8-mbit: amax = a18 unused address inputs should be treated as rfu. ad[15:0] input / output address-data multiplexed inputs/ outputs: global device signals. during ad-mux write cycles, ad[15:0] are used to input the lower address followed by commands or data. during ad-mux read cycles, ad[15:0] are used to input the lower address followed by read-data output. during nand accesses, ad[7:0] is used to input commands, address-data, or write-data, and output read-data. ad[15:0] are high-z when the device is deselected or its output is disabled. adv# input address valid: flash- and synchronous psram-specific signal; low-true input. during synchronous flash read operations, the address is latched on the rising edge of f-adv#, or on the first rising edge of f-clk after f-adv# goes low for devices that support up to 108 mhz, or on the last rising edge of f-clk after f-adv# goes low for devices that support up to 133 mhz. in an asynchronous flash read operation, the address is latched on the rising edge of adv#. control signals f[4:1]-ce# input flash chip enable: flash-specific signal; low-true input. when low, f-ce# selects the associated flash memory die. when high, f-ce# deselects the associated flash die. flash die power is reduced to standby levels, and its data and f-wait outputs are placed in a high-z state. ? f1-ce# is dedicated to flash die #1. ? f[4:2]-ce# are dedicated to flash die #4 through #2, respectively, if present. otherwise, any unused flash chip enable should be treated as rfu. ? for nor/nand stacked device, f1-ce# selects nor die #1, f2-ce# selects nor die #2 while f4-ce# selects nand die #1 and nand die #2 using virtual chip-select scheme, f3-ce# selects nand die #3 if present.
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 32 document number: 309823-005us clk input clock: flash- and synchronous psram-specific input signal. clk synchronizes the flash and/or synchronous psram with the system clock during synchronous operations. f[2:1]-oe# input flash output enable: flash-specific signal; low-true input. when low, f-oe# enables the output drivers of the selected flash die. when high, f-oe# disables the output drivers of the selected flash die and places the output drivers in high-z. ? for nor only stacked device, f[2:1]-oe# are common to all nor dies in the device. ? for nor/nand stacked device, f1-oe# enables all nor dies, f2-oe# selects all nand dies if present. 2 r-oe# input ram output enable: psram- and sram-specific signal; low-true input. when low, r-oe# enables the output drivers of the selected memory die. when high, r-oe# disables the output drivers of the selected memory die and places the output drivers in high-z. 1 f-rst# input flash reset: flash-specific signal; low-true input. when low, f-rst# resets internal operations and inhibits writes. when high, f-rst# enables normal operation. wait output wait: flash -and synchronous psram-specific signal; configurable true-level output. when asserted, wait indicates invalid output data. when deasserted, wait indicates valid output data. ? wait is driven whenever the flash or the synchronous psram is selected and its output enable is low. ? wait is high-z whenever flash or the synchronous psram is deselected, or its output enable is high. f-we# input flash write enable: flash-specific signal; low-true input. when low, f-we# enables write operations for the enabled flash die. address and data are latched on the rising edge of f-we#. r-we# input ram write enable: psram- and sram-specific signal; low-true input. when low, r-we# enables write operations for the selected memory die. data is latched on the rising edge of r-we#. 1 f- wp[2:1]# input flash write protect: flash-specific signals; low-true inputs. when low, f-wp# enables the lock-down mechanism. when high, f-wp# overrides the lock-down function, enabling locked-down blocks to be unlocked with the unlock command. ? f-wp1# is dedicated to flash die #1. ? f-wp2# is common to all other flash dies, if present. otherwise it is rfu. ? for nor/nand stacked device, f-wp1# selects all nor dies, while f-wp2# selects all nand dies. f-dpd input flash deep power-down: flash-specific signal; configurable-true input. when enabled in the ecr, f-dpd is used to enter and exit deep power-down mode. n-cle input nand command latch enable: nand-specific signal; high-true input. when high, n-cle enables commands to be latched on the rising edge of n-we#. 1 n-ale input nand address latch enable: nand-specific signal; high-true input. when high, n-ale enables addresses to be latched on the rising edge of n-we#. 1 n-re# input nand read enable: nand-specific signal; low-true input. when low, n-re# enables the output drivers of the selected nand die. when high, n-re# disables the output drivers of the selected nand die and places the output drivers in high-z. 1, 2 n-ry/by# output nand ready/busy: nand-specific signal; low-true output. when low, n-ry/by# indicates the nand is busy performing a read, program, or erase operation. when high, n-ry/by# indicates the nand device is ready. 1 n-we# input nand write enable: nand-specific signal; low-true input. when low, n-we# enables write operations for the enabled nand die. 1, 4 p-cre input psram control register enable: synchronous psram-specific signal; high-true input. when high, p-cre enables access to the refresh control register (p-rcr) or bus control register (p-bcr). when low, p-cre enables normal read or write operations. 1, 3 table 9. signal descriptions for x16c / x16c ad-mux ballout (sheet 2 of 3) symbol type signal descriptions notes
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 33 notes: 1. only available on stacked device combinations with nand, sram, and/or lpsdram die. otherwise treated as rfu. 2. f2-oe# and n-re# share the same package ball at location h9. only one signal function is available, depending on the stacked device combination. 3. p-cre and p-mode# share the same package ball at location k9. only one signal function is available, depending on the stacked device combination. 4. s-cs1# and n-we# share the same package ball at location j2. only one signal function is available, depending on the stacked device combination. 5. the f2-vcc signal applies to a nand flash die if one exists; if not, the f2-vcc signal applies to the nor flash die. p-mode# input psram mode#: asynchronous only psram-specific signal; low-true input. when low, p-mode# enables access to the configuration register, and to enter or exit low-power mode. when high, p-mode# enables normal read or write operations. 1, 3 p[2:1]-cs# input psram chip select: psram-specific signal; low-true input. when low, p-cs# selects the associated psram memory die. when high, p-cs# deselects the associated psram die. psram die power is reduced to standby levels, and its data and wait outputs are placed in a high-z state. ? p1-cs# is dedicated to psram die #1. ? p2-cs# is dedicated to psram die #2. otherwise, any unused psram chip select should be treated as rfu. 1 s-cs1# s-cs2 input sram chip selects: sram-specific signals; s-cs1# low-true input, s-cs2 high-true input. when both s-cs1# and s-cs2 are asserted, the sram die is selected. when either s-cs1# or s-cs2 is deasserted, the sram die is deselected. 1, 4 r-ub# r-lb# input ram upper/lower byte enables: psram- and sram-specific signals; low-true inputs. when low, r-ub# enables dq[15:8] and r-lb# enables dq[7:0] during psram or sram read and write cycles. when high, r-ub# masks dq[15:8] and r-lb# masks dq[7:0]. 1 power signals f-vpp power flash program/erase voltage: flash specific. f-vpp supplies program or erase power to the flash die. f[2:1]-vcc power flash core power supply: flash specific. f[2:1]-vcc supplies the core power to the flash die. for nor/nand stacked device, f1-vcc is dedicated for all nor dies, f2-vcc is dedicated for all nand dies. 5 vccq power i/o power supply: global device i/o power. vccq supplies the device input/output driver voltage. p-vcc power psram core power supply: psram specific. p-vcc supplies the core power to the psram die. 1 s-vcc power sram power supply: sram specific. s-vcc supplies the core power to the sram die. 1 vss ground device ground: global ground reference for all signals and power supplies. connect all vss balls to system ground. do not float any vss connections. du ? do not use: this ball should not be connected to any power supplies, signals, or other balls. this ball can be left floating. rfu ? reserved for future use: reserved by intel for future device functionality and enhancement. this ball must be left floating. table 9. signal descriptions for x16c / x16c ad-mux ballout (sheet 3 of 3) symbol type signal descriptions notes
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 34 document number: 309823-005us 4.5 signal ballouts x16 split bus 4.5.1 x16 split bus (165-ball) ballout, non-mux figure 13. x16 split bus (165 active ball) electrical ballout, non-mux 12 3456789101112 adu b: d-a2 b: d-a0 b: d-ba0 b: d-a11 b: d-a12 b: d-a8 b: d-a6 b: d-a4 du a bdu a: f-a15 b: d-a3 b: d-a1 b: d-ba1 b: d-we# b: d-a13 b: d-a9 b: d-a7 b: d-a5 rfu du b c a: f-a13 a: f-a14 a: f-a16 a: vss a: f3- ce# / n2- ce# a: f4- ce# / n1-ce# b: d -ck e b : d-a14 a: vss rfu a: f-d7 / n-adq7 a: f-d14 / n-adq14 c da: f-a12 a: f-a22 a: f2-ce# b: d-a10 b: d-vc c b: d1- ce# b: d2- ce# b: d- clk# b: d-clk a: vss a: f-d15 / n-adq15 a: f-d6 / n-adq6 d ea: f-a11 a: f-a21 a: n-r/b# a: f-dpd rfu b: d- ras# b: d- cas# rfu a: f- wait a: vccq rfu a: f-d13 / n-adq13 e f a: f-a10 a: f-a20 a: f-we# a: vss depop (index) depop (rfu) depop (rfu) a: f2- vcc / n-vcc a: vss a: vccq a: vss a: f-d5 / n-adq5 f ga: f-a9 a: f-a26 a: f-wp1# a: f- wp2# / n-wp# rfu depop (rfu) depop (rfu) b: d-vcc rfu a: f- adv# a: f-d12 / n-adq12 a: f-d4 / n-adq4 g h a: f-a8 a: f-a24 a: f-a25 a: vss a: f1-ce# depop (rfu) depop (rfu) a: f1- vcc a: vss rfu rfu a: f-clk h ja: f-a18 a: f-a19 a: f-a23 a: n-cle a: f2- vcc / n- vc c depop (rfu) depop (rfu) rfu rfu a: f-oe# a: f-d10 / n-adq10 a: f-d11 / n-adq11 j k a: f-a7 a: f-a17 rfu a: vss b: d-vc c depop (rfu) depop (rfu) rfu a: vss a: vccq a: vss a: f-d3 / n-adq3 k la: f-a5 a: f-a6 a: n-ale a: n-we# a: f1-vcc a: n-re# rfu a: f-vpp a: f- rst# a: vccq rfu a: f-d2 / n-adq2 l m a: f-a3 a: f-a4 rfu b: d- vddq b: d-dm0 b: d - vddq b: d- vddq b: d- dm1 b: d- vddq a: vss a: f-d1 / n-adq1 a: f-d9 / n-adq9 m na: f-a1 a: f-a2 b: d-vss b: d- dqs0 b: d-vss a: vss b: d-vss b: d- dqs1 b: d-vss rfu a: f-d8 / n-adq8 a: f-d0 / n-adq0 n p du a: f-a0 b: d-d1 b: d-d3 b: d-d5 b: d-d7 b: d-d8 b: d-d10 b: d-d12 b: d-d14 rfu du p r du b: d-d0 b: d-d2 b: d-d4 b: d-d6 b: d-d9 b: d-d11 b: d-d13 b: d-d15 du r 12 3456789101112 top view - ball side down pin 1 b5173 -01
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 35 4.6 signal descriptions x16 split bus table 10. signal descriptions, x16 split bus, non-mux (sheet 1 of 4) symbol type signal descriptions note s address and data signals, non-mux f-a[max:0] input flash address: flash device signals. dedicated address inputs for flash memory die during read and write operations. ? 2-gbit: amax = a26 ? 1-gbit: amax = a25 ? 512-mbit: amax = a24 ? 256-mbit: amax = a23 ? 128-mbit: amax = a22 unused address inputs are rfu. d-a[max:0] input lpsdram address: lspdram device signals. dedicated address inputs for lpsdram memory die during read and write operations. ? a[12:0] are the row and a[9:0] are the column addresses for 512-mbit lpsdram. ? a[12:0] are the row and a[8:0] are the column addresses for 256-mbit lpsdram. ? a[11:0] are the row and a[8:0] are the column addresses for 128-mbit lpsdram. unused address inputs are rfu. f-dq[15:0] input/ output flash data input/outputs: flash device signals. ? inputs flash data and commands during write cycles. ? outputs data during read cycles. ? data signals are high-z when the device is deselected or its output is disabled. d-dq[15:0] input/ output lpsdram data input/outputs: lpsdram device signals. ? inputs lpsdram data and commands during write cycles. ? outputs data during read cycles. ? data signals are high-z when the device is deselected or its output is disabled. address and data signals, a/d mux f-a[max:16] input address: flash device signals. shared address inputs for all flash memory die during read and write operations. ? 2-gbit: amax = a26 ? 1-gbit: amax = a25 ? 512-mbit: amax = a24 ? 256-mbit: amax = a23 ? 128-mbit: amax = a22 unused address inputs should be treated as rfu. f-adq[15:0] input / output address-data multiplexed inputs/ outputs: ad-mux flash lower address and data signals; lpsdram data signals. during ad-mux flash write cycles, adq[15:0] are used to input the lower address followed by commands or write-data. during ad-mux flash read cycles, adq[15:0] are used to input the lower address followed by read-data output. during lpsdram accesses, adq[15:0] are used to input commands and write-data during write cycles or to output read-data during read cycles. during nand accesses, adq[7:0] are used to input commands, address, or write-data, and to output read-data. adq[15:0] are high-z when the flash is deselected or its output is disabled. control signals
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 36 document number: 309823-005us f-adv# input flash address valid: flash-specific signal; low-true input. during synchronous flash read operations, the address is latched on the rising edge of f- adv#, or on the first rising edge of f-clk after f-adv# goes low for devices that support up to 108 mhz, or on the last rising edge of f-clk after f-adv# goes low for devices that support up to 133 mhz. in an asynchronous flash read operation, the address is latched on the rising edge of f- adv#. f[4:1]-ce# input flash chip enable: flash-specific signal; low-true input. when low, f-ce# selects the associated flash memory die. when high, f-ce# deselects the associated flash die. flash die power is reduced to standby levels, and its data and f-wait outputs are placed in a high-z state. ? f1-ce# is dedicated to flash die #1. ? f[4:2]-ce# are dedicated to flash die #4 through #2, respectively, if present. otherwise, treat any unused flash chip enable as rfu. ? when nand is used, f4-ce# is dedicated for nand die 1 and nand die 2. otherwise, this is rfu. f-clk input flash clock: flash-specific signal; configurable active-edge input. f-clk synchronizes the flash memory with the system clock during synchronous operations. d-clk input lpsdram clock: lpsdram-specific signal; rising active-edge input. d-clk synchronizes the lpsdram and ddr lpsdram with the system clock. 1 d-clk# input ddr lpsdram clock: ddr lpsdram-specific signal; falling active-edge input. d-clk# synchronizes the ddr lpsdram with the system clock. 1 f-oe# input flash output enable: flash-specific signal; low-true input. ? when low, oe# enables the output drivers of the selected flash die. ? when high, oe# disables the output drivers of the selected flash die and places the output drivers in high-z. f-rst# input flash reset: flash-specific signal; low-true input. ? when low, f-rst# resets internal operations and inhibits writes. ? when high, f-rst# enables normal operation. f-wait output flash wait: flash-specific signal; configurable-true output. when asserted, f-wait indicates invalid output data. ? f-wait is driven whenever f-ce# and oe# is low. ? f-wait is high-z whenever f-ce# or oe# is high. f-we# input flash write enable: flash-specific signal; low-true input. when low, we# enables write operations for the selected flash die. n-we# input nand write enable: nand-specific signal; low-true input. when low, we# enables write operations for the selected nand die. 1 d-we# input lpsdram write enable: lpsdram-specific signal; low-true input. d-we#, together with a[max:0], d-ba[1:0], d-cke, d-cs#, d-cas#, and d-ras#, define the lpsdram command or operation. d-we# is sampled on the rising edge of d-clk. 1 f-wp[2:1]# input flash write protect: flash-specific signals; low-true inputs. when low, f-wp# enables the lock-down mechanism. when high, f-wp# overrides the lock-down function, enabling locked-down blocks to be unlocked with the unlock command. ? f-wp1# is dedicated to flash die #1. ? f-wp2# is used for nand die when available. otherwise, this signal is for all other nor die. f-dpd input flash deep power-down: flash-specific signal; configurable-true input. when enabled in the ecr, f-dpd is used to enter or exit deep power-down mode. n-cle input nand command latch enable: nand-specific signal; high-true input. when high, n-cle enables commands to be latched on the rising edge of we#. 1 table 10. signal descriptions, x16 split bus, non-mux (sheet 2 of 4) symbol type signal descriptions note s
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 37 n-ale input nand address latch enable: nand-specific signal; high-true input. when high, n-ale enables addresses to be latched on the rising edge of we#. 1 n-r/b# output nand ready/busy: nand-specific signal; low-true output. ? when low, n-ry/by# indicates the nand device is busy performing a read, program, or erase operations. ? when high, n-ry/by# indicates the nand device is ready. 1 n-re# output nand read enable: nand-specific signal; drives the data onto the flash bus after the falling edge of n-re#. this signal increments the internal column address and reads out each data. 1 d-cke input lpsdram clock enable: lpsdram-specific signal; high-true input. ? when high, d-cke indicates that the next d-clk edge is valid. ? when low, d-cke indicates that the next d-clk edge is invalid and the selected lpsdram die is suspended. 1 d-ba[1:0] input lpsdram bank select: lpsdram-specific input signals. d-ba[1:0] selects one of four banks in the lpsdram die. 1 d-ras# input lpsdram row address strobe: lpsdram-specific signal; low-true input. d-ras#, together with a[max:0], d-ba[1:0], d-cke, d-cs#, d-cas#, and d-we#, define the lpsdram command or operation. d-ras# is sampled on the rising edge of d-clk. 1 d-cas# input lpsdram column address strobe: lpsdram-specific signal; low-true input. d-cas#, together with a[max:0], d-ba[1:0], d-cke, d-cs#, d-ras#, and d-we#, define the lpsdram command or operation. d-cas# is sampled on the rising edge of d-clk. 1 d[2:1]-ce# input lpsdram chip enable: lpsdram-specific signal; low-true input. when low, d-cs# selects the associated lpsdram memory die and starts the command input cycle. when d-cs# is high, commands are ignored but operations continue. ? d-cs#, together with a[max:0], d-ba[1:0], d-cke, d-ras#, d-cas#, and d-we#, define the lpsdram command or operation. d-cs# is sampled on the rising edge of d-clk. ? d[2:1]-cs# are dedicated to lpsdram die #2 and die #1, respectively, if present. otherwise, treat any unused lpsdram chip selects as rfu. 1 d-dm[1:0] input lpsdram data mask: lpsdram-specific signal; high-true input. when high, d-dm[1:0] controls masking of input data during writes and output data during reads. ? d-dm1 corresponds to the data on dq[15:8]. ? d-dm0 corresponds to the data on dq[7:0]. 1 d-dqs1 d-dqs0 input / output lpsdram upper/lower data strobe: ddr lpsdram-specific input/output signals. d-dqs1 and d-dqs0 provide as output the read data strobes, and as input the write data strobes. ? d-dqs1 corresponds to the data on dq[15:8]. ? d-dqs0 corresponds to the data on dq[7:0]. 1 power signals f-vpp power flash program/erase voltage: flash specific. f-vpp supplies program or erase power to the flash die. f[2:1]-vcc power flash core power supply: flash specific. f-vcc supplies the core power to the flash die. ? f1-vcc is dedicated for nor die. ? f2-vcc is used for nand die when available. otherwise, this signal is for nor die. (when nand is available, the f2-vcc signal is named n-vcc.) d-vcc power lpsdram core power supply: lpsdram specific. d-vcc supplies the core power to the lpsdram die. 1 vccq power flash i/o power supply: global device i/o power. vccq supplies the device input/output driver voltage to the flash die. table 10. signal descriptions, x16 split bus, non-mux (sheet 3 of 4) symbol type signal descriptions note s
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 38 document number: 309823-005us d-vddq power lpsdram i/o power supply: global device i/o power. vddq supplies the device input/output driver voltage to the lpsdram die. 1 vss ground flash device ground: global ground reference for all flash signals and power supplies. connect all a: vss balls to system ground. do not float any vss connections. d-vss ground lpsdram device ground: global ground reference for all lpsdram signals and power supplies. connect all b: d-vss balls to system ground. do not float any vss connections. 1 du ? do not use: do not connect this ball to any power supplies, signals, or other balls. this ball can be left floating. rfu ? reserved for future use: reserved by intel for future device functionality and enhancement. this ball must be left floating. notes: 6. available only on stacked device combinations with nand, and/or lpsdram die. otherwise, treat the signal as rfu. table 10. signal descriptions, x16 split bus, non-mux (sheet 4 of 4) symbol type signal descriptions note s
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 39 5.0 maximum ratings and operating conditions 5.1 absolute maximum ratings warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. notice: this document contains information available at the time of its release. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. table 11. absolute maximum ratings parameter min max unit conditions notes temperature under bias expanded ?30 +85 c ? ? storage temperature ?65 +125 c ? ? f-vcc voltage ?2.0 v ccq + 2.0 v ? 1,2 vccq ?2.0 v ccq + 2.0 v ? 1,3 voltage on any input/output signal (except vcc, vccq, and vpp) ?2.0 v ccq + 2.0 v ? 1,3 f-vpp voltage ?2.0 +11.5 v ? 1,3 i sh output short circuit current ? 100 ma ? 4 v pph time ? 80 hours 5 block program/erase cycles: main blocks 100,000 ? cycles f-vpp = v cc or f-vpp = v pph 5 notes: 1. voltage is referenced to v ss . 2. during signal transitions, minimum dc voltage may undershoot to ?2.0 v for periods < 20 ns; maximum dc voltage may overshoot to v cc (max) + 2.0 v for periods < 20 ns. 3. during signal transitions, minimum dc voltage may undershoot to ?1.0 v for periods < 20 ns; maximum dc voltage may overshoot to v ccq (max) + 1.0 v for periods < 20 ns. 4. output shorted for no more than one second. no more than one output shorted at a time. 5. operation beyond this limit may degrade performance.
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 40 document number: 309823-005us 5.2 operating conditions warning: operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. table 12. operating conditions symbol description min max unit conditions t c operating temperature (case temperature) ?30 +85 c ? v cc vcc supply voltage +1.7 +2.0 v ? v ccq i/o supply voltage +1.7 +2.0 v ? v ppl programming voltage (logic level) +0.9 +2.0 v ? v pph factory programming voltage (high level) +8.5 +9.5 v ?
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 41 6.0 electrical characteristics 6.1 dc current specifications table 13. dc current specifications, 90 nm and 65 nm (sheet 1 of 3) sym parameter density 1.7 v ? 2.0 v unit test conditions notes typ max i li input load current ? 1 a v cc = v cc max v ccq = v ccq max v in = v ccq or v ss 1 i lo output leakage current ? 1 a v cc = v cc max v ccq = v ccq max v in = v ccq or v ss i ccs v cc standby 256-mbit (90 nm) 512-mbit (90 nm) 1-gbit (65 nm) 35 50 70 95 120 185 a v cc = v cc max v ccq = v ccq max ce# = v ccq rst# = v ccq or gnd (for i ccs ) wp# = v ih 1,2 i ccaps aps 256-mb (90 nm) 512-mb (90 nm) 1-gbit (65 nm) 35 50 70 95 120 185 a v cc = v cc max v ccq = v ccq max ce# = v ssq rst# = v ccq all inputs are at rail to rail (v ccq or v ssq ). ? i dpd dpd 256-mb (90 nm) 512-mb (90 nm) 1-gbit (65 nm) 230a v cc = v cc max v ccq = v ccq max ce# = v ccq rst# = v ccq ecr[15] = v ccq dpd = v ccq or v ssq all inputs are at rail to rail (v ccq or v ssq ). 8 i ccr average v cc read: asynchronous single word read f = 5 mhz, (1 clk) 256-mb (90 nm) 512-mb (90 nm) 1-gbit (65 nm) 25 30 ma v cc = v cc max ce# = v il oe# = v ih inputs: v il or v ih 1,3, 4,5 i ccr average v cc read: page mode read f = 13 mhz, (17 clk) burst = 16 word 256-mb (90 nm) 512-mb (90 nm) 1-gbit (65 nm) 11 15 ma v cc = v cc max ce# = v il oe# = v ih inputs: v il or v ih 1,3, 4,5
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 42 document number: 309823-005us i ccr average v cc read: synchronous burst read f = 66 mhz, lc = 7 burst = 8 word 256-mb (90 nm) 512-mb (90 nm) 1-gbit (65 nm) 22 32 ma v cc = v cc max ce# = v il oe# = v ih inputs: v il or v ih 1,3, 4,5 burst = 16 word 256-mb (90 nm) 512-mb (90 nm) 1-gbit (65 nm) 19 26 ma burst = continuous 256-mb (90 nm) 512-mb (90 nm) 1-gbit (65 nm) 25 34 ma i ccr average v cc read: synchronous burst read f = 108 mhz, lc = 10 burst = 8 word 256-mb (90 nm) 512-mb (90 nm) 1-gbit (65 nm) 26 36 ma v cc = v cc max ce# = v il oe# = v ih inputs: v il or v ih 1,3, 4,5 burst = 16 word 256-mb (90 nm) 512-mb (90 nm) 1-gbit 23 30 ma burst = continuous 256-mb (90 nm) 512-mb (90 nm) 1-gbit (65 nm) 30 42 ma i ccr average v cc read: synchronous burst read f = 133 mhz, lc = 13 burst = 8 word 256-mb (90 nm) 512-mb (90 nm) 1-gbit (65 nm) 26 35 ma v cc = v cc max ce# = v il oe# = v ih inputs: v il or v ih 1,3, 4,5 burst = 16 word 256-mb (90 nm) 512-mb (90 nm) 1-gbit (65 nm) 24 33 ma burst = continuous 256-mb (90 nm) 512-mb (90 nm) 1-gbit (65 nm) 33 46 ma i ccw, i cce i ccbc v cc program v cc erase v cc blank check 35 50 ma v pp = v ppl or v pp = v pph , program/erase in progress 1,3,4, 5,7 table 13. dc current specifications, 90 nm and 65 nm (sheet 2 of 3) sym parameter density 1.7 v ? 2.0 v unit test conditions notes typ max
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 43 6.2 dc voltage specifications i ccws, i cces v cc program suspend v cc erase suspend 256-mb (90 nm) 512-mb (90 nm) 1-gbit (65 nm) 35 50 70 95 120 185 a ce# = v ccq ; suspend in progress 1,3,6 i pps, i ppws, ippes v pp standby v pp program suspend v pp erase suspend 0.2 5 a v pp = v ppl; suspend in progress 3 i ppr v pp read 2 15 a v pp v cc 3 i ppw v pp program 0.05 0.1 ma v pp = v ppl = v pph, program in progress 3 i ppe v pp erase 0.05 0.1 ma v pp = v ppl = v pph, erase in progress 3 i ppbc v pp blank check 0.05 0.1 ma v pp = v ppl = v pph, blank check in progress 3 notes: 1. all currents are rms unless noted. typical values at typical v cc , t c = +25 c. 2. i ccs is the average current measured over any 5 ms time interval 5 s after ce# is deasserted. 3. sampled, not 100% tested. 4. v cc read + program current is the sum of v cc read and v cc program currents. 5. v cc read + erase current is the sum of v cc read and v cc erase currents. 6. i cces is specified with the device deselected. if device is read while in erase suspend, current is i cces plus i ccr 7. i ccw , i cce measured over typical or max times specified in section 7.4, ?program and erase characteristics? on page 67 8. i dpd is the current measured 40 s after entering dpd. table 13. dc current specifications, 90 nm and 65 nm (sheet 3 of 3) sym parameter density 1.7 v ? 2.0 v unit test conditions notes typ max table 14. dc voltage specifications symbol parameter v ccq 1.7 v ? 2.0 v unit test condition notes min max v il input low voltage 0 0.4 v ?1 v ih input high voltage v ccq ?0.4 v ccq ?? v ol output low voltage ? 0.1 v cc = v cc min v ccq = v ccq min i ol = 100 a ? v oh output high voltage v ccq ?0.1 ? v cc = v cc min v ccq = v ccq min i oh = ?100 a ? v pplk v pp lock-out voltage ? 0.4 ? 2 v lko v cc lock voltage 1.0 ? ? ? v lkoq v ccq lock voltage 0.9 ? ? ? notes: 1. during signal transitions, voltage can undershoot to ?1.0 v and overshoot to maximum v ccq +1.0 v for durations of < 2 ns. 2. v pp v pplk inhibits erase and program operations. do not use v ppl and v pph outside their valid ranges.
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 44 document number: 309823-005us 6.3 capacitance table 15. capacitance symbol parameter min typ max unit condition notes c in input capacitance (address, clk, ce#, oe#, adv#, we#, wp#, dpd and rst#) 246 pf v in = 0 - 2.0 v 1,2 c out output capacitance (data and wait) 2 5 6 v out = 0 - 2.0 v notes: 1. t c = +25c, f = 1 mhz. 2. sampled, not 100% tested.
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 45 7.0 nor flash ac characteristics timing symbols used in the timing diagrams within this document conform to the following conventions: note: exceptions to this conventions include tacc and tapa. tacc is a generic timing symbol that refers to the aggregate initial-access delay as determined by tavqv, telqv, and tglqv (whichever is satisfied last) of the flash device. tapa is specified in the flash device datasheet, and is the address-to-data delay for subsequent page-mode reads. figure 14. timing symbol notation convention e t l q v source signal target state source state target signal table 16. codes for timing signals and timing states signal code state code address a high h data - read q low l data - write d high-z z chip enable (ce#) e low-z x output enable (oe#) g valid v write enable (we#) w invalid i address valid (adv#) v ? ? reset (rst#) p ? ? clock (clk) c ? ? wait t ? ?
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 46 document number: 309823-005us 7.1 ac test conditions note: ac test inputs are driven at v ccq for logic ?1? and 0.0 v for logic ?0?. input/output timing begins and ends at v ccq /2. notes: 1. see the following table for component values. 2. test configuration component value for worst case speed conditions. 3. c l includes jig capacitance. figure 15. ac input/output reference waveform v ccq 0v v ccq /2 v ccq /2 t e s t p o i n t s input output v ih v il t rise/f al l table 17. ac input requirements symbol parameter frequency min max unit condition t rise/fall inputs rise/fall time (address, clk, ce#, oe#, adv#, we#, wp#) 133mhz, 108mhz 0.3 1.2 ns v il to v ih or v ih to v il @66mhz 0 3 t askw address-address skew 0 3 at v ccq /2 figure 16. transient equivalent testing load circuit device under test out c l table 18. test configuration component value for worst case speed conditions test configuration c l (pf) 1.7 v standard test 30 2.0 v standard test 30
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 47 7.2 read specifications the m18 device includes read specifications for the following speeds and voltage levels: ? 512-mbit device: 108 mhz, v ccq = 1.7 v to 2.0 v ? 1-gbit device: 108 mhz, v ccq = 1.7 v to 2.0 v ? 256-mbit device: 133 mhz, v ccq = 1.7 v to 2.0 v devices which support frequencies up to 133 mhz must meet additional timing specifications for synchronous reads (for address latching with clk) as listed in ta b l e 2 0 . figure 17. clock input ac waveform clk [c] v ih v il r203 r202 r201 table 19. ac read, 512-mbit, 1-gbit, 108 mhz, v ccq = 1.7 v to 2.0 v (sheet 1 of 2) nbr. symbol parameter 1 96 ns unit notes min max asynchronous specifications r1 t avav read cycle time 96 ? ns ? r2 t avqv address to output valid ? 96 ns ? r3 t elqv ce# low to output valid ? 96 ns ? r4 t glqv oe# low to output valid ? 20 ns 2 r5 t phqv rst# high to output valid ? 150 ns ? r6 t elqx ce# low to output in low-z 0 ? ns 3 r7 t glqx oe# low to output in low-z 0 ? ns 2,3 r8 t ehqz ce# high to output in high-z ? 9 ns 3 r9 t ghqz oe# high to output in high-z ? 9 ns r10 t oh output hold from first occurring address, ce#, or oe# change 0 ? ns r11 t ehel ce# pulse width high 7 ? ns ? r12 t eltv ce# low to wait valid ? 11 ns ? r13 t ehtz ce# high to wait high z ? 9 ns 3 r14 t ghtv oe# high to wait valid (ad-mux only) ? 7 ns ? r15 t gltv oe# low to wait valid ? 7 ns ?
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 48 document number: 309823-005us r16 t gltx oe# low to wait in low-z 0 ? ns 3 r17 t ghtz oe# low to wait in high-z (non-mux only) 0 9 ns 3 latching specifications r101 t avvh address setup to adv# high 5 ? ns ? r102 t elvh ce# low to adv# high 9 ? ns ? r103 t vlqv adv# low to output valid ? 96 ns ? r104 t vlvh adv# pulse width low 7 ? ns ? r105 t vhvl adv# pulse width high 7 ? ns ? r106 t vhax address hold from adv# high 5 ? ns 4 r107 t vhgl adv# high to oe# low (ad-mux only) 7 ? ns ? r108 t apa page address access (non-mux only) ? 15 ns ? r111 t phvh rst# high to adv# high 30 ? ns ? clock specifications r200 f clk clk frequency ? 108 mhz ? r201 t clk clk period 9.26 ? ns ? r202 t ch/cl clk high/low time 3.5 ? ns ? r203 t fclk/rclk clk fall/rise time 0.3 1.2 ns ? synchronous specifications r301 t avch address setup to clk high 5 ? ns ? r302 t vlch adv# low setup to clk high 5 ? ns ? r303 t elch ce# low setup to clk high 5 ? ns ? r304 t chqv clk to output valid ? 7 ns ? r305 t chqx output hold from clk high 2 ? ns ? r306 t chax address hold from clk high 5 ? ns 4 r307 t chtv clk high to wait valid ? 7 ns ? r311 t chvl clk high to adv# setup 2 ? ns ? r312 t chtx wait hold from clk 2 ? ns ? notes: 1. see figure 15, ?ac input/output reference waveform? on page 46 for timing measurements and maximum allowable input slew rate. 2. oe# may be delayed by up to t elqv ? t glqv after ce#?s falling edge without impact to t elqv. 3. sampled, not 100% tested. 4. address hold in synchronous burst mode is t chax or t vhax , whichever timing specification is satisfied first. table 19. ac read, 512-mbit, 1-gbit, 108 mhz, v ccq = 1.7 v to 2.0 v (sheet 2 of 2) nbr. symbol parameter 1 96 ns unit notes min max
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 49 table 20. ac read, 256-mbit, 133 mhz, v ccq = 1.7 v to 2.0 v (sheet 1 of 2) nbr. symbol parameter 1 96 ns units notes min max asynchronous specifications r1 t avav read cycle time 96 ? ns ? r2 t avqv address to output valid ? 96 ns ? r3 t elqv ce# low to output valid ? 96 ns ? r4 t glqv oe# low to output valid ? 7 ns 2 r5 t phqv rst# high to output valid ? 150 ns ? r6 t elqx ce# low to output in low-z 0 ? ns 3 r7 t glqx oe# low to output in low-z 0 ? ns 2,3 r8 t ehqz ce# high to output in high-z ? 7 ns 3 r9 t ghqz oe# high to output in high-z ? 7 ns r10 t oh output hold from first occurring address, ce#, or oe# change 0 ? ns r11 t ehel ce# pulse width high 7 ? ns ? r12 t eltv ce# low to wait valid ? 8 ns ? r13 t ehtz ce# high to wait high z ? 7 ns 3 r14 t ghtv oe# high to wait valid (ad-mux only) ? 5.5 ns ? r15 t gltv oe# low to wait valid ? 5.5 ns ? r16 t gltx oe# low to wait in low-z 0 ? ns 3 r17 t ghtz oe# high to wait in high-z (non-mux only) 0 7 ns 3 latching specifications r101 t avvh address setup to adv# high 5 ? ns ? r102 t elvh ce# low to adv# high 7 ? ns ? r103 t vlqv adv# low to output valid 96 ns ? r104 t vlvh adv# pulse width low 7 ? ns ? r105 t vhvl adv# pulse width high 7 ? ns ? r106 t vhax address hold from adv# high 5 ? ns ? r107 t vhgl adv# high to oe# low (ad-mux only) 2 ? ns ? r108 t apa page address access (non-mux only) ? 15 ns ? r111 t phvh rst# high to adv# high 30 ? ns ? clock specifications r200 f clk clk frequency ? 133 mhz ? r201 t clk clk period 7.5 ? ns ? r202 t ch/cl clk high/low time 3.2 ? ns ? r203 t fclk/rclk clk fall/rise time 0.3 1.2 ns ? synchronous specifications r301 t avch address setup to clk high 2 ? ns ? r302 t vlch adv# low setup to clk high 2 ? ns ?
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 50 document number: 309823-005us 7.2.1 timings: non mux device, async read note: wait polarity in figure is low-true (rcr10 = 0, default). wait deasserted during asynchronous reads. r303 t elch ce# low setup to clk high 2.5 ? ns ? r304 t chqv clk to output valid ? 5.5 ns ? r305 t chqx output hold from clk high 2 ? ns ? r306 t chax address hold from clk high 2 ? ns ? r307 t chtv clk high to wait valid ? 5.5 ns ? r311 t chvl clk high to adv# setup 2 ? ns ? r312 t chtx wait hold from clk high 2 ? ns ? r313 t chvh adv# hold from clk high 2 ? ns ? r314 t chgl clk to oe# low (ad-mux only) 2 ? ns ? r315 t acc read access time from address latching clock 96 ? ns ? r316 t vlvh adv# pulse width low for sync reads 1 2 clks ? r317 t vhch adv# high to clk high 2 ? ns ? notes: 1. see figure 15, ?ac input/output reference waveform? on page 46 for timing measurements and maximum allowable input slew rate. 2. oe# may be delayed by up to t elqv ? t glqv after ce#?s falling edge without impact to t elqv. 3. sampled, not 100% tested. table 20. ac read, 256-mbit, 133 mhz, v ccq = 1.7 v to 2.0 v (sheet 2 of 2) nbr. symbol parameter 1 96 ns units notes min max figure 18. async single-word read: adv# latch r10 r7 r6 r17 r15 r9 r4 r8 r3 r106 r101 r105 r105 r2 r1 address [max:4] [a] a[3:0] adv#[v] ce# [e} oe# [g ] wait [t] data [d/q]
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 51 note: wait polarity in figure is low-true (rcr10 = 0, default). wait deasserted during asynchronous reads. 7.2.2 timings: non mux device, sync read, 512-mbit, 1-gbit, 108 mhz / notes: 1. wait polarity in figure is low-true (rcr10 = 0, default) 2. this figure illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by oe# and ce# deassertion after the first word in the burst. 3. address latched on rising clk edge after adv# low. figure 19. async page-mode read timing q0 q1 q14 q15 r108 r9 r7 r17 r15 r10 r4 r8 r3 r106 r101 r105 r105 r1 r1 r2 a ddress[max:4] [a] a[3:0] adv#[v] ce# [e] oe# [g] wait [t ] dat a [ d/q] figure 20. sync single-word array/non-array read, 512-mbit, 1-gbit, 108 mhz latency count r9 r8 r305 r304 r4 r13 r307 r16 r7 r303 r102 r3 r104 r106 r101 r104 r105 r105 r2 r306 r301 clk [c] a ddress [a] adv# [v] ce# [e] oe# [g] wait [t] data [d/q]
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 52 document number: 309823-005us notes: 1. at the end of word line (eowl); the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 16-word boundary aligned. 2. wait polarity in figure is low-true (rcr10 = 0, default). 3. address latched on rising clk edge after adv# low. . notes: 1. wait polarity in figure is low-true (rcr10 = 0, default). 2. 8-word and 16-word burst are always wrap-only. 3. address latched on rising clk edge after adv# low. figure 21. continuous burst read: output delay at eowl, 512-mbit, 1-gbit, 108 mhz r305 r305 r305 r305 r304 r4 r7 r312 r307 r15 r303 r102 r3 r106 r105 r105 r101 r2 r304 r304 r304 r306 r302 r301 clk [c] a ddress [a] adv# [v] ce# [e] oe# [g] wait [t] data [d/q] figure 22. sync burst-mode unaligned 8-word burst read, 512-mbit, 1-gbit, 108 mhz a q 3 q 4 q 5 q 6 q 7 q 0 q1 q2 r1 7 r30 7 r305 r30 4 r4 r7 r307 r15 r303 r3 r106 r10 2 r105 r105 r101 r2 r306 r302 r301 clk [ c] a ddress [a] adv# [ v] ce# [ e] oe# [g] w ai t [ t] data [d/q]
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 53 7.2.3 timings: non mux device, sync read, 256-mbit, 133 mhz notes: 1. address is latched on first clk edge after adv# assertion, associated setup and hold timings shown. 2. wait polarity in figure is low-true (rcr10 = 0, default). . notes: 1. address is latched on the second rising clk edge after adv# assertion, associated setup and hold timing shown. 2. wait polarity in figure is low-true (rcr10 = 0, default). figure 23. sync array/non-array read, 256-mbit, 133 mhz clkn clk1 addr latched clk0 r311 r304 r305 r304 r305 r315 r304 r307 r15 r316 r317 r313 r316 r303 r306 r301 r302 clk [c] a ddr ess [a] ce# [e] adv# [v] oe# [g] wait [t] data [d/q] figure 24. sync array/non-array read: adv# max low pulse width, 256-mbit, 133 mhz clkn clk1 addr latched clk0 r304 r305 r315 r304 r307 r15 r316 r313 r316 r311 r303 r306 r301 r317 r302 clk [c] a ddress [a] ce# [e] adv# [v] oe# [g] wait [t] data [d/q]
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 54 document number: 309823-005us notes: 1. at the end of word line (eowl); the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 16-word boundary aligned. 2. wait polarity in figure is low-true (rcr10 = 0, default). 3. address is latched on the first rising clk edge after adv# assertion, associated setup and hold timing shown. . notes: 1. wait polarity in figure is low-true (rcr10 = 0, default). 2. 8-word and 16-word burst reads are always wrapped. 3. address is latched on the second rising clk edge after adv# assertion, associated setup and hold timing shown. figure 25. continuous burst read: output delay at eowl, 256-mbit, 133 mhz clkn clk1 addr latched c lk0 r311 r304 r305 r304 r305 r315 r304 r307 r15 r316 r317 r313 r316 r303 r306 r301 r 302 clk [c] a ddr ess [a] ce# [e] adv# [v] oe# [g] wait [t] data [d/q] figure 26. sync burst-mode unaligned 8-word burst read, 256-mbit, 133 mhz q2 q3 q4 q5 q6 q7 q0 q1 clkn clk1 addr latched clk0 r9 r8 r13 r304 r305 r315 r304 r307 r15 r316 r313 r316 r311 r303 r306 r301 r317 r302 clk [c] a ddress [a] ce# [e] adv# [v] oe# [g] wait [t] data [d/q]
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 55 7.2.4 timings: ad-mux device, async read note: wait polarity in figure is low-true (rcr10 = 0, default). wait is deasserted during asynchronous reads. 7.2.5 timings: ad-mux device, sync read, 512-mbit, 1-gbit, 108 mhz notes: 1. wait polarity in figure is low-true (rcr10 = 0, default).. 2. this figure illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by oe# and ce# deassertion after the first word in the burst. 3. address latched on first clk edge after adv# low. figure 27. async word read a q r4 r13 r12 r9 r7 r107 r8 r101 r106 r3 r2 a[m ax:16] a /d q[15:0] adv# [v] ce# [e] oe# [g] wait [t] figure 28. sync single-word array/non-array read, 512-mbit, 1-gbit, 108 mhz latency count a a q r13 r15 r12 r9 r107 r4 r8 r102 r303 r106 r105 r302 r105 r305 r304 r3 r101 r2 r301 r306 clk [c] a[max:16] a /dq[15:0] adv# [v] ce# [e] oe# [g] wait [t]
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 56 document number: 309823-005us notes: 1. at the end of word line (eowl); the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 16-word boundary aligned. 2. wait polarity in figure is low-true (rcr10 = 0, default). 3. address latched on first clk edge after adv# low. . notes: 1. wait polarity in figure is low-true (rcr10 = 0, default). 2. address latched on first clk edge after adv# low. figure 29. continuous burst read: output delay at eowl, 512-mbit, 1-gbit, 108 mhz fir st access latency a q q q q q r 307 r307 r 307 r15 r12 r 107 r4 r 102 r 303 r 302 r305 r304 r305 r 304 r3 r 301 clk [c] a[max:16] a /dq[15:0] adv# [v] ce# [e] oe# [g] wait [t] figure 30. sync burst-mode unaligned 16-word burst read, 512-mbit, 1-gbit, 108 mhz latency count a a q1 q1 q15 q0 r13 r14 r307 r307 r15 r12 r9 r 107 r4 r 102 r303 r302 r305 r304 r3 r301 clk [c] a[max:16] a /dq[15:0] adv# [v] ce# [e] oe# [g] wait [t]
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 57 7.2.6 timings: ad-mux device, sync read, 256-mbit, 133 mhz notes: 1. address is latched on the first rising clk edge after adv# assertion, associated setup and hold timing shown. 2. wait polarity in figure is low-true (rcr10 = 0, default). . notes: 1. address is latched on the second rising clk edge after adv# assertion, associated setup and hold timing shown. 2. wait polarity in figure is low-true (rcr10 = 0, default). 3. 8-word and 16-word burst reads are always wrapped. figure 31. sync array or non-array read, 256-mbit, 133 mhz clkn clk1 addr latched clk0 r311 r307 r15 r12 r107 r316 r317 r313 r316 r303 r305 r304 r306 r301 r302 clk [c] a [max:16] [a] a/d q[15:0] ce# [e] adv# [v] oe# [g] wait [t] figure 32. sync unaligned 8-word burst read: adv# max low pulse width, 256-mbit, 133 mhz q2 q7 q0 q1 clkn clk1 addr latched clk0 r307 r 307 r15 r12 r9 r4 r314 r316 r313 r316 r311 r8 r303 r 304 r306 r 301 r317 r 302 clk [c] a [max:16] [a] a/d q [15:0] ce# [e] ad v# [v] oe# [g] wait [t]
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 58 document number: 309823-005us notes: 1. at the end of word line (eowl); the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 16-word boundary aligned 2. wait polarity in figure is low-true (rcr10 = 0, default). 3. address is latched on the first rising clk edge after adv# assertion, associated setup and hold timing shown. figure 33. continuous burst read: output delay at eowl, 256-mbit, 133 mhz clkn clk1 addr latched clk0 r311 r307 r307 r15 r12 r107 r 316 r 317 r313 r 316 r303 r305 r304 r306 r 301 r302 clk [c] a [max:16] [a] a/d q[15:0] ce# [e] adv# [v] oe# [g] wait [t]
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 59 7.3 write specifications the m18 device includes write specifications for the following speeds and voltage levels: ? 512-mbit device: 108 mhz, v ccq = 1.7 v to 2.0 v ? 1-gbit device: 108 mhz, v ccq = 1.7 v to 2.0 v ? 256-mbit device: 133 mhz, v ccq = 1.7 v to 2.0 v table 21. ac write specifications number symbol parameter (1, 2) min max units notes w1 t phwl rst# high recovery to we# low 150 ? ns 1,2,3 w2 t elwl ce# setup to we# low 0 ? ns 1,2 w3 t wlwh we# write pulse width low 40 ? ns 1,2,4 w4 t dvwh data setup to we# high 40 ? ns 1,2 w5 t avwh address setup to we# high 40 ? ns w6 t wheh ce# hold from we# high 0 ? ns w7 t whdx data hold from we# high 0 ? ns w8 t whax address hold from we# high (non-mux only) 0 ? ns w9 t whwl we# pulse width high 20 ? ns 1,2,5 w10 t vpwh vpp setup to we# high 200 ? ns 1,2,3,7 w11 t qvvl vpp hold from status read 0 ? ns w12 t qvbl wp# hold from status read 0 ? ns w13 t bhwh wp# setup to we# high 200 ? ns w14 t whgl we# high to oe# low 0 ? ns 1,2,8 w15 t vlwh adv# low to we# high (ad-mux only) 55 ? ns 1,2 w16 t whqv we# high to read valid t avqv +30 ? ns 1,2,3,9 write to synchronous read specifications w19 t whch we# high to clock high 15 ? ns 1,2,3,6,9 w27 t whel we# high to ce# low 9 ? ns 1,2,3,6,9 w28 t whvl we# high to adv# low 7 ? ns 1,2,3,6,9 bus write with active clock specifications w21 t vhwl adv# high to we# low ? 27 ns 1,2,10,11 w22 t chwl clock high to we# low ? 27 ns notes: 1. write timing characteristics during erase suspend are the same as write-only operations. 2. a write operation can be terminated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width low (t wlwh or t eleh ) is defined from ce# or we# low (whichever occurs last) to ce# or we# high (whichever occurs first). hence, t wlwh = t eleh = t wleh = t elwh . 5. write pulse width high (t whwl or t ehel ) is defined from ce# or we# high (whichever occurs first) to ce# or we# low (whichever occurs last). hence, t whwl = t ehel = t whel = t ehwl ). 6. t whch must be met when transitioning from a write cycle to a synchronous burst read. in addition there must be a ce# toggle after we# goes high. 7. vpp and wp# should be at a valid level until erase or program success is determined. 8. when doing a read status operation following any command that alters the status register data, w14 is 20ns. 9. add 10ns if the write operations results in a rcr or block lock status change, for the subsequent read operation to reflect this change. 10. this specification is applicable only if the part is configured in synchronous mode and an active clock is running. either t vhwl or t chwl must be met depending on the whether the address is latched on adv# or clk. 11. these specifications are not applicable to 133 mhz devices.
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 60 document number: 309823-005us 7.3.1 timings: non mux device, async write note: wait polarity in figure is low-true (rcr10 = 0, default). wait deasserted during asynchronous reads and high-z during writes. figure 34. write to write figure 35. async read to write w13 w1 w7 w4 w7 w4 w3 w9 w3 w9 w3 w3 w6 w2 w6 w2 w8 w8 w5 w5 a ddress [a] ad v# ce# [e} we# [w] oe# [g] data [d/q] rst# [p] wp# q d r5 w7 w4 r10 r7 r6 r17 r15 w6 w3 w3 w2 r9 r4 r8 r3 w8 w5 r1 r2 r1 a ddress [a] ce# [e] oe# [g] we# [w] wait [t] data [d/q] rst# [p]
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 61 7.3.2 timings: non mux device, sync write, 512-mbit, 1-gbit, 108 mhz notes: 1. wait polarity in figure is low-true (rcr10 = 0, default). wait is high-z during write operations. 2. clock is ignored during write operation. figure 36. write to async read figure 37. sync read to write, 512-mbit, 1-gbit, 108 mhz d q w1 r9 r8 r4 r3 r2 w7 w4 r17 r15 w14 w3 w3 r10 r11 r11 w6 w2 r1 r1 w8 w5 a ddress [a] adv# [v] ce# [e} we# [w] oe# [g] wait [t] data [d/q] rst# [p] latency count q d d w7 r8 r305 r304 r7 r13 r307 r16 w1 5 w9 w19 w8 w9 w3 w2 2 w21 w3 w2 r9 r4 w6 r11 r11 r303 r3 w20 r104 r104 r106 r102 r105 r105 w1 8 w5 r101 r2 r306 r302 r301 clk [c] a ddress [a] adv# [v] ce# [e] oe# [g] we # wait [t] data [d/q]
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 62 document number: 309823-005us note: wait polarity in figure is low-true (rcr10 = 0, default). 7.3.3 timings: non mux device, sync write, 256-mbit, 133 mhz note: wait polarity in figure is low-true (rcr10 = 0, default). figure 38. write to sync read, 512-mbit, 1-gbit, 108 mhz d q q w1 r304 r305 r304 r3 w7 w4 r307 r1 5 r4 w16 w1 9 w3 w3 r1 1 r303 r1 1 w6 w2 r104 r106 r104 r306 w8 w5 r302 r301 r2 clk a ddress [a] adv# ce# [e} we # [w] oe# [g] wait [t] data [d/q] rst # [p] figure 39. sync read to write, 256-mbit, 133 mhz addr latched clk clkn clk1 addr latched clk0 r311 r311 r11 r304 r305 r315 r304 w21 r17 r13 r307 r15 r316 r317 r313 r316 r316 r317 r313 r316 r303 r306 r301 r302 r302 clk [c] a ddress [a] ce# [e] adv# [v] oe# [g] wait [t] we# data [d/q]
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 63 note: wait polarity in figure is low-true (rcr10 = 0, default). 7.3.4 timings: ad-mux device, async write note: wait polarity in figure is low-true (rcr10 = 0, default). figure 40. write to sync read, 256-mbit, 133 mhz d q address latched clk r305 r315 r304 w7 w4 r307 r15 w19 w3 w3 r11 r11 w6 w2 r316 r313 r302 r311 r306 r301 w8 w5 clk[c] a ddress [a] adv#[v] ce# [e] we# [w] oe# [g] wait [t] data [d/q] figure 41. write to write a d a d w1 3 w1 w3 w9 w3 w9 w3 w3 w6 w2 w6 w2 w15 w8 w7 w4 w5 a[m a x- 1 6 ] [a] a /dq[15-0] [a/d] adv# [v] ce# [e] we# [w] oe# [g] rst# [p] wp#
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 64 document number: 309823-005us note: wait polarity in figure is low-true (rcr10 = 0, default). note: wait polarity in figure is low-true (rcr10 = 0, default). figure 42. async read to write a q a d r13 r12 r13 r12 w6 w4 w3 w3 w2 r9 r107 r8 r3 w7 w5 r10 r2 r1 r1 a[max:16] a /dq [15:0] ce# [e] adv#[v] oe# [g] we# [w] wait[t] figure 43. write to async read a d a d a q w1 r13 r12 r13 r12 r9 r7 r4 w14 r107 w3 w9 w3 w18 w9 w3 w3 r8 r3 r11 r11 w6 w2 w2 w20 r2 w21 w15 w8 w7 w4 w5 a[max-16] a /dq[15-0] adv# [v] ce# [e] we# [w] oe# [g] wait [t] rst# [p]
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 65 7.3.5 timings: ad-mux device, sync write, 512-mbit, 1-gbit, 108 mhz note: wait polarity in figure is low-true (rcr10 = 0, default). note: wait polarity in figure is low-true (rcr10 = 0, default). figure 44. sync read to write, 512-mbit, 1-gbit, 108 mhz a a q q a d a d r301 w15 w9 w7 w3 w9 w3 w2 r12 r13 r15 r12 r4 r11 r11 w20 w4 w5 r3 r7 r306 r2 clk [c] a[max:16] a /dq[15:0] adv# [v] ce# [e] oe# [g] wait [t] we# [w] figure 45. write to sync read, 512-mbit, 1-gbit, 108 mhz latency count d q q w1 r304 r305 r304 r3 w7 w4 r307 r12 r4 w1 9 w3 w3 r1 1 r303 r1 1 w6 w2 r104 r106 r104 r306 w8 w5 r302 r301 r2 clk a ddress [a] adv# ce# [e} we# [w] oe# [g] wai t [t ] data [d/q] rst # [p]
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 66 document number: 309823-005us 7.3.6 timings: ad-mux device, sync write, 256-mbit, 133 mhz note: wait polarity in figure is low-true (rcr10 = 0, default). note: wait polarity in figure is low-true (rcr10 = 0, default). figure 46. sync read to write, 256-mbit, 133 mhz q d clkn clk1 addr latched clk0 r14 r13 r15 r12 r107 w15 w3 w3 w21 r316 r 317 r313 r311 r316 r303 w7 w8 r304 r 305 r304 w5 r306 r301 r302 clk a [max:16] [a] a/d q[15:0] ce# [e] adv# [v] we#[e] oe# [g] wait [t] figure 47. write to sync read, 256-mbit, 133 mhz a d a q clkn clk1 addr latched clock r307 r15 r12 r13 r12 r4 r107 w27 w19 w5 w3 w21 w3 r303 w6 w2 r313 r316 r316 r311 r304 r305 r304 r301 w7 w4 r306 r317 r302 clk[c] a [max:16] [a] a/d q[15:0] adv# [v] ce# [e] we# [w] oe# [g] wait[t]
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 67 7.4 program and erase characteristics table 22. program-erase characteristics, 256-mbit, 512-mbit and 1-gbit (sheet 1 of 2) nbr. symbol parameter v ppl /v pph unit notes density min typ max conventional word programming w200 t prog/w program time single word (first word) 256-mbit (90 nm) 512-mbit (90 nm) 1-gbit (65 nm) ? 115 230 s 1,2 single word (subsequent word) 256-mbit (90 nm) 512-mbit (90 nm) 1-gbit (65 nm) ? 50 230 buffered programming w200 t prog/w program time single word 256-mbit (90 nm) 512-mbit (90 nm) 1-gbit (65 nm) ? 250 500 s 1 w250 t prog/pb one buffer (512 words) 256-mbit (90 nm) 512-mbit (90 nm) 1-gbit (65 nm) ? 2.15 2.15 1.64 4.3 4.3 3.3 ms buffered enhanced factory programming w451 t befp/w program time single word 256-mbit (90 nm) 512-mbit (90 nm) 1-gbit (65 nm) ? 4.2 4.2 3.2 ? s 1,3,4 w452 t befp/setup buffered efp setup 256-mbit (90 nm) 512-mbit (90 nm) 1-gbit (65 nm) 5?? 1 erasing and suspending w501 t ers/mab erase time 128-kword main array block 256-mbit (90 nm) 512-mbit (90 nm) 1-gbit (65 nm) ?0.94 s 1
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 68 document number: 309823-005us w600 t susp/p suspend latency program suspend 256-mbit (90 nm) 512-mbit (90 nm) 1-gbit (65 nm) ?2030 s 1 w601 t susp/e erase suspend 256-mbit (90 nm) 512-mbit (90 nm) 1-gbit (65 nm) ?2030 1 blank check w702 t bc/mb blank check main array block 256-mbit (90 nm) 512-mbit (90 nm) 1-gbit (65 nm) ?3.2?ms 1 notes: 1. typical values measured at t c = +25 c and nominal voltages. performance numbers are valid for all speed versions. sampled, but not 100% tested. 2. first and subsequent words refer to first word and subsequent words in control mode programming region. 3. averaged over entire device. 4. befp not validated at v ppl . table 22. program-erase characteristics, 256-mbit, 512-mbit and 1-gbit (sheet 2 of 2) nbr. symbol parameter v ppl /v pph unit notes density min typ max
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 69 7.5 reset specifications table 23. reset specifications nbr. symbol parameter min max unit notes p1 t plph rst# pulse width low 100 ns 1,2,3,4,7 p2 t plrh rst# low to device reset during erase ? 25 s 1,3,4,7 rst# low to device reset during program ? 25 1,3,4,7 p3 t vccph v cc power valid to rst# de-assertion (high) 300 ? 1,4,5,6 notes: 1. these specifications are valid for all device versions (packages and speeds). 2. the device may reset if t plph is < t plph min , but this is not guaranteed. 3. not applicable if rst# is tied to vccq. 4. sampled, but not 100% tested. 5. if rst# is tied to the v cc supply, device will not be ready until t vccph after v cc v cc min. 6. if rst# is tied to any supply/signal with v ccq voltage levels, the rst# input voltage must not exceed v cc until v cc v cc (min). 7. reset completes within t plph if rst# is asserted while no erase or program operation is executing. figure 48. reset operation timing ( a) reset during read mode (b) reset during program or block erase p1 p2 (c) reset during program or block erase p1 p2 v ih v il v ih v il v ih v il rst# [p] rst# [p] rst# [p] abort complete abort complete v cc 0v v cc (d) vcc power-up to rst# high p1 r5 p2 p3 p2 r5 r5
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) ds november 2006 70 document number: 309823-005us 7.6 deep power down specifications note: dpd pin is low-true (ecr14 = 0) note: dpd pin is low-true (ecr14 = 0) table 24. deep power down specifications nbr. symbol parameter min max unit notes s1 t slsh ( t shsl) dpd asserted pulse width 100 ? ns 1,2,3 s2 t ehsh ( t ehsl) ce# high to dpd asserted 0 ? s 1,2 s3 t shel (t slel) dpd deasserted to ce# low 75 ? 1,2 s4 t phel rst# high during dpd state to ce# low (dpd deasserted to ce# low) 75 ? 1,2 notes: 1. these specifications are valid for all device versions (packages and speeds). 2. sampled, but not 100% tested. 3. dpd must remain asserted for the duration of deep power down mode. dpd current levels are achieved 40 s after entering the dpd mode. figure 49. deep power down operation timing s3 s1 s2 dpd [s] ce# [e] rst# [p] figure 50. reset during deep power down operation timing s4 s2 rst# [p] dpd [s] ce# [e]
intel strataflash ? cellular memory (m18) intel strataflash ? cellular memory (m18) november 2006 ds document number: 309823-005us 71

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